121 lines
9.5 KiB
Markdown
121 lines
9.5 KiB
Markdown
# Disconnected serial subset
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The core supports disconnected normal-mode transfers, external-clock waiting, and general-purpose pins.
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Internal clocks shift pulled-high input at nominal GBA rates. No link partner is emulated.
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External clock edges, multiplayer, UART, Joybus communication, and GPIO interrupts remain unsupported.
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Unsupported activity remains diagnostic rather than reporting a fabricated completion.
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## Registers
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- `SIODATA32` at `0x04000120` holds the 32-bit shift register. Byte lanes and halfword accesses are supported.
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- `SIODATA8` at `0x0400012a` holds the 8-bit shift register; its upper byte reads zero.
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Each transfer shifts only its selected data register. The other register retains its value.
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- `SIOCNT` at `0x04000128` retains normal 8/32-bit mode, IRQ configuration, clock selection, and the output-data bit.
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The retained mask is `0x508b`. The disconnected serial input is high, except when a general-purpose output drives it low.
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Start bit 7 requests a transfer. Bit 0 selects external or internal clock; bit 1 selects the internal rate.
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Completion or software cancellation clears start. Multiplayer/UART mode bit 13 remains unsupported.
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- `RCNT` at `0x04000134` retains mode bits, interrupt configuration, output latches, and pin directions with mask `0xc1ff`.
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With bit 15 clear, bits 8 and 14 are writable latches without GPIO interrupt or Joybus effects.
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With bit 15 set, bit 14 selects Joybus; otherwise bit 8 enables GPIO interrupts. Both active configurations remain diagnostic.
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In general-purpose mode, each input reads high through its pull-up. Each output reads its output latch.
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`RCNT=0x8000` therefore reads back as `0x800f`, not `0x8000`.
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Normal-mode low-byte pin readback remains unmapped rather than guessed.
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- `JOYCNT` permits clearing already-empty status flags. Joybus interrupt enable is unsupported.
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- `JOY_RECV` and `JOY_TRANS` permit only zero writes and zero readback for reset initialization.
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Nonzero writes return an explicit error. Joybus status and data-transfer side effects are not implemented.
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GPIO means general-purpose input/output. UART means universal asynchronous receiver/transmitter.
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No external serial device is connected. Only an enabled internal serial clock can shift data or generate a completion IRQ.
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Configuration that hardware accepts in other modes can still be rejected by this intentionally limited subset.
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## External-clock waiting
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In normal 8-bit or 32-bit mode, setting start with clock-source bit 0 clear requests externally clocked communication.
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No device is connected, so no external clock edges arrive. Start remains set; data does not shift and no completion IRQ occurs.
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The internal-rate selector, bit 1, does not supply clocks when bit 0 is clear.
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CPU cycles, timer overflows, display events, and DMA activity cannot manufacture external serial clocks.
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Repeated start writes do not complete the request. Software can cancel it by clearing start, including through BIOS serial reset.
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General-purpose mode does not shift serial data. A retained external-clock start bit has no link-port effect there.
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Returning to normal mode still cannot complete a transfer without external clock edges.
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Selecting internal clock while an unshifted request is pending starts a fresh nominal bit period.
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This is a disconnected waiting model, not an implementation of a connected link or an external clock-input API.
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Original tests cover both widths, rate settings, control lanes, cancellation, GPIO selection, HALT/STOP, and ARM/Thumb stores.
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DMA tests distinguish its own completion IRQ from a serial IRQ. Invalid word/block stores cannot leave a partial start request.
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## Internal clocks and completion
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Normal mode shifts most-significant bit first. At each nominal sampling edge, the selected register shifts left and receives a one.
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The disconnected SI input is high. Completion therefore leaves `0xff` or `0xffffffff`, without inventing peer data.
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Reads between edges expose the partially shifted value. SO waveforms and normal-mode RCNT pin samples remain unmodeled.
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At the nominal 16,777,216 Hz system clock:
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| SIOCNT bit 1 | Cycles per bit | 8-bit transfer | 32-bit transfer |
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| --- | --- | --- | --- |
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| 0 | 64 | 512 cycles | 2,048 cycles |
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| 1 | 8 | 64 cycles | 256 cycles |
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The first sample occurs one full bit period after activation. Selecting internal clock for an unshifted external request uses this same rule.
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A repeated start write with unchanged width/clock fields preserves the current phase and remaining bit count.
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A width/clock change before any bit has shifted starts a fresh period. Data writes before that first bit preserve the phase.
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Software cancellation clears progress but retains already shifted data.
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Whole-access writes merge control and data lanes before applying start/cancel behavior; byte writes remain separate accesses.
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Completion clears start and latches IF bit 7 when SIOCNT bit 14 is enabled at the final edge.
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IE, IME, and CPSR.I gate wake-up or delivery, not request latching. Clearing IF acknowledges the request.
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A completed request does not reassert IF without another transfer.
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HALT continues internal shifting and bounds its idle batch at serial completion. STOP freezes the bit phase and remaining count.
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Only keypad wake is implemented for STOP; serial GPIO wake still requires its missing external-input model.
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### Bus timing and validation
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Serial state shares the timer/audio transaction during CPU instructions, IRQ entry, and DMA units.
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Each access observes all elapsed source/data cycles through its bus-completion phase.
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A start write excludes its preceding cycles. A load excludes its trailing internal cycle.
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IF reads and acknowledgements include serial completion through that access, alongside timer requests.
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Successful steps commit serial state and requests once. Failed steps discard speculative shifts, writes, and completion IRQs.
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The display/capture scheduler does not clock serial again after that commit.
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CPU-only stepping can change registers but does not advance serial clocks.
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Block-store preflight simulates ordered access phases on temporary timing/device copies before committing any write.
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Validation can therefore accept reconfiguration when an earlier request completes before the write reaches the bus.
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The actual transfers then execute once from the original state. Other IF sources and DMA completion flags remain independent.
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### Bounded behavior
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After any bit has shifted, changes to width, clock selection/rate, or the selected data register remain diagnostic while start stays set.
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Selecting GPIO during an internally clocked request also remains diagnostic. Clear start before these operations.
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IRQ-enable and idle SO configuration writes remain supported without restarting progress.
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These limits also apply to BIOS services that write serial registers; cancel active transfers before requesting serial reset.
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Unverified live reconfiguration is not silently approximated.
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The period arithmetic follows documented GBA rates. Activation phase, mid-transfer register visibility, and exact pin edges lack physical-hardware validation.
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No external pin waveform, cable, connected partner, or serial-device protocol is implemented.
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Original tests cover individual shifts, batching, cancellation, IRQ gating, HALT/STOP, bus phases, DMA, capture independence, and rollback.
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## BIOS reset
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RegisterRamReset always clears the low halfword of SIODATA32, even without bit 5.
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The upper halfword remains unchanged in this functional subset.
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With bit 5 selected, the firmware clears SIOCNT and SIODATA8, selects general-purpose inputs, and clears the supported Joybus reset registers.
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It uses ordinary ARM bus stores, not a host-side reset bypass.
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Clearing SIOCNT cancels a pending external-clock request. Unselected serial reset leaves that request pending.
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Original tests cover independent byte lanes, input pull-ups, output directions, reset flag selection, and explicit unsupported operations.
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Whole-access and block-store validation prevent a rejected control value from committing preceding bytes or registers.
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Static RCNT mode rejection uses the complete high byte. Live-transfer validation additionally uses staged serial state.
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Mode-gating tests cover every high-byte value, previous modes, low-byte preservation, CPU stores, DMA retries, and unchanged interrupt state.
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Inactive configuration bits do not wake HALT. RCNT word accesses still reject the unmapped padding at `0x04000136`.
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## References
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- [GBATEK reset functions](https://problemkaputt.de/gbatek-bios-reset-functions.htm): reset flags, general-purpose selection, and the unconditional SIODATA32 side effect.
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- [GBATEK normal serial mode](https://problemkaputt.de/gbatek-sio-normal-mode.htm): data widths, MSB-first shifting, rates, pulled-high SI, start/completion, IRQ selection, and external-clock waiting.
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- [GBATEK mode summary](https://problemkaputt.de/gbatek-sio-control-registers-summary.htm): RCNT/SIOCNT mode selection.
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- [mGBA serial implementation at 3a5e34be](https://github.com/mgba-emu/mgba/blob/3a5e34be33dc7f8f707e5bc9db69e8a430046f21/src/gba/sio.c): cross-checked normal transfer-duration arithmetic and completion IRQ handling. Its no-driver scheduled completion and zero receive data are not copied; they do not establish disconnected hardware behavior.
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- [GBATEK](https://mgba-emu.github.io/gbatek/): GBA general-purpose pin directions, internal pull-ups, SI falling-edge interrupts, and the SIO mode-selection table.
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- [mGBA BIOS implementation at 3a5e34be](https://github.com/mgba-emu/mgba/blob/3a5e34be33dc7f8f707e5bc9db69e8a430046f21/src/gba/bios.c): functional serial reset defaults, not copied source.
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Exact firmware write ordering and hardware pin timing remain unverified.
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