Commit graph

28 commits

Author SHA1 Message Date
0xrsydn
a8944d1d5f feat(bios): implement selective RegisterRamReset service
Execute SWI 0x01 through original ARM code. Clear selected work RAM, palette RAM, VRAM, and OAM; force blank; reset supported display, DMA, timer, and interrupt registers through normal bus writes. Preserve caller state and excluded BIOS work RAM apart from the common SWI frame.

Reject serial/sound reset flags before display or reset writes. Document the supported subset, timer counter behavior, DMA ordering, and RAM caller hazards. Add fifteen tests covering memory flags and boundaries, I/O defaults, rendering, register preservation, hidden device latches, diagnostics, and device progress.

Validated on Darwin arm64: 720 default and 709 core-only tests in debug and release; formatting, Clippy, rustdoc, ten native window smoke tests, and CPU/timer demos pass.
2026-10-05 15:54:07 +07:00
0xrsydn
2dfab137a6 feat(bios): implement SoftReset restart service
Execute SWI 0x00 through original ARM code. Read the restart flag before clearing 512 bytes of BIOS work RAM, reset System/SVC/IRQ stacks and specified registers, then branch to ROM or EWRAM in ARM System mode.

Keep device state and clocks active, preserve unrelated CPU banks, and document the deterministic IRQ-masked restart status. Add eleven tests for every flag byte, ARM/Thumb and User/System callers, exact memory bounds, bank state, restart execution, DMA/timers, and unsupported exception callers.

Validated on Darwin arm64: 705 default and 694 core-only tests in debug and release; formatting, Clippy, rustdoc, ten native window smoke tests, and CPU/timer demos pass.
2026-10-05 15:36:07 +07:00
0xrsydn
f60db7e43b feat(bios): implement background and object affine services
Execute BgAffineSet and ObjAffineSet through original ARM routines with a mathematically generated sine table. Preserve caller state, validate record spans and strides, and use normal bus writes for background registers and sprite matrices.

Add independent matrix/origin references, all-phase coverage, rendering integration, diagnostics, stack and DMA checks. Extend image construction with multiple literal pools and reserved table bounds. Document formats and compatibility limits.

Validated on Darwin arm64: 694 default and 683 core-only tests in debug and release; formatting, Clippy, rustdoc, ten native window smoke tests, and CPU/timer demos pass.
2026-10-05 15:22:54 +07:00
0xrsydn
1edaa4151d feat(bios): implement fixed-point ArcTan and ArcTan2 services
Add SWI 0x09 and 0x0a as original ARM routines. Evaluate the fixed-point angle polynomial with wrapped products, reduce ArcTan2 ratios with integer division, and handle axes and quadrants. Require sign-extended 16-bit inputs and preserve non-result caller registers.

Add 15 regression tests for fixed-point and floating-point references, signed limits, rounding, quadrant boundaries, caller flags, stack bounds, repeated calls, and DMA/IRQ progress. Validate 671 default and 660 core-only tests in debug and release, plus all 10 native Darwin ARM64 window smoke tests.
2026-10-05 14:37:08 +07:00
0xrsydn
f0e5240d44 feat(bios): decode Huffman streams through ARM instructions
Implement SWI 0x13 for 4-bit and 8-bit symbols. Traverse forward-offset trees using MSB-first input words and pack symbols into complete output words. Validate visited edges, leaf widths, alignment, output lengths, and address bounds.

Add 21 regression tests with independent tree serialization and path encoding, deep/max-size trees, word-boundary refills, malformed input, partial failures, caller state, and DMA/IRQ progress. Validate 656 default and 645 core-only tests in debug and release, plus all 10 native Darwin ARM64 window smoke tests.
2026-10-05 14:18:18 +07:00
0xrsydn
3ebc1f03d0 feat(bios): implement byte and halfword differential filters
Add SWI 0x16, 0x17, and 0x18 as original ARM routines. Reconstruct samples with modular addition and byte or halfword output. Validate headers, alignment, lengths, and address ranges; preserve earlier completed writes on failure.

Add 17 regression tests for sample round trips, wraparound, large byte lengths, caller state, partial failures, bus behavior, and DMA/IRQ progress. Validate 635 default and 624 core-only tests in debug and release, plus all 10 native Darwin ARM64 window smoke tests.
2026-10-05 13:14:00 +07:00
0xrsydn
f9a426a11e feat(desktop): integrate native macOS windows controls and smoke tests
Expose core modules and original demo images. Add CLI modes, native windows, scripted smoke tests, and the pinned minifb focus workaround.
2026-10-05 12:58:40 +07:00
0xrsydn
189240d9b4 feat(demo): exercise timer setup and IRQ handlers 2026-10-05 12:58:40 +07:00
0xrsydn
0b3935800a feat(demo): exercise HBlank DMA palette changes 2026-10-05 12:58:40 +07:00
0xrsydn
c6a447d554 feat(demo): exercise background and sprite mosaic controls 2026-10-05 12:58:40 +07:00
0xrsydn
bb409f27b1 feat(demo): exercise windows blending and brightness 2026-10-05 12:58:40 +07:00
0xrsydn
52194cd38b feat(demo): exercise Mode 4 and 5 page switching 2026-10-05 12:58:39 +07:00
0xrsydn
cf9ee0ca65 feat(demo): exercise affine transforms and raster distortion 2026-10-05 12:58:39 +07:00
0xrsydn
169fab9bf6 feat(demo): run CPU-driven bitmap tile and sprite scenes
Add original ARM graphics programs, input controls, DMA initialization, and a bounded frame runner.
2026-10-05 12:58:39 +07:00
0xrsydn
0280563430 feat(bios): expand packed units with BitUnPack
Add SWI 0x10, packed-unit widths, conditional offsets, complete word stores, and independent bit-level tests.
2026-10-05 12:58:39 +07:00
0xrsydn
5984551784 feat(bios): decode run-length streams through ARM instructions
Add RLUnCompWram and RLUnCompVram with block bounds, word-independent buffering, and device-progress tests.
2026-10-05 12:58:39 +07:00
0xrsydn
17e9351371 feat(bios): decode LZ77 streams through ARM instructions
Add byte and buffered-halfword output, overlapping references, argument diagnostics, and a reusable output routine.
2026-10-05 12:58:39 +07:00
0xrsydn
096bcfe314 feat(bios): implement division and integer square root
Add Div, DivArm, and Sqrt with emitted ARM algorithms and independent arithmetic references.
2026-10-05 12:58:39 +07:00
0xrsydn
04e4599677 feat(bios): add original boot IRQ waits and memory services
Generate original ARM firmware for minimal boot, IRQ callbacks, HALT, IntrWait, CpuSet, and CpuFastSet.
2026-10-05 12:58:39 +07:00
0xrsydn
bfab05b34d feat(video): bound per-row sprite preparation work
Apply nominal 1210/954-cycle allowances, affine setup costs, OAM-order allocation, and partial sprite prefixes.
2026-10-05 12:58:38 +07:00
0xrsydn
52c77193cb feat(video): capture scanlines and prepare sprites one row ahead
Add cycle40 preparation, deferred diagnostics, HBlank capture, VBlank presentation, and affine history tests.
2026-10-05 12:58:38 +07:00
0xrsydn
1cba1510d0 feat(video): render regular and affine sprites
Add OAM sampling, affine canvases, tile mapping, priority metadata, OBJ windows, and mosaic composition.
2026-10-05 12:58:38 +07:00
0xrsydn
45b45e5c52 feat(video): track background and sprite mosaic state
Add vertical mosaic counters and background/sprite sampling regressions.
2026-10-05 12:58:38 +07:00
0xrsydn
9d14dd7cf4 feat(video): track windows and compose color effects
Add persistent window comparators, region masks, alpha blending, and brightness effects.
2026-10-05 12:58:38 +07:00
0xrsydn
fad034ae74 feat(video): render tiled affine and bitmap backgrounds
Add Mode 0-5 composition, palettes, tile maps, affine sampling, and framebuffer diagnostics.
2026-10-05 12:58:38 +07:00
0xrsydn
bb6784615a feat(machine): schedule display DMA IRQs and HALT
Integrate nominal bus timing, device clocks, display events, DMA transfers, keypad state, and interrupt delivery.
2026-10-05 12:58:38 +07:00
0xrsydn
156f1eb839 feat(memory): map GBA memory and device registers
Add memory mirrors, video-bus write rules, I/O latches, timers, and interrupt registers.
2026-10-05 12:58:38 +07:00
0xrsydn
535c69e09f feat(cpu): implement ARM7TDMI ARM and Thumb execution
Add ALU, transfers, banked status, exceptions, instruction timing, and CPU regression tests.
2026-10-05 12:58:38 +07:00