336 lines
35 KiB
Markdown
336 lines
35 KiB
Markdown
# Testing and validation
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Run native macOS validation from the project directory:
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```sh
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direnv exec . cargo fmt --all --check
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direnv exec . cargo clippy --locked --all-targets -- -D warnings
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direnv exec . cargo test --locked
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direnv exec . cargo test --locked --release
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direnv exec . cargo build --locked --release
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file target/release/gameboy-rust
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./target/release/gameboy-rust --smoke-test
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./target/release/gameboy-rust --graphics-smoke-test
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./target/release/gameboy-rust --tile-smoke-test
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./target/release/gameboy-rust --affine-smoke-test
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./target/release/gameboy-rust --affine-raster-smoke-test
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./target/release/gameboy-rust --bitmap4-smoke-test
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./target/release/gameboy-rust --bitmap5-smoke-test
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./target/release/gameboy-rust --effects-smoke-test
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./target/release/gameboy-rust --mosaic-smoke-test
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./target/release/gameboy-rust --raster-smoke-test
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./target/release/gameboy-rust --cpu-demo
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./target/release/gameboy-rust --timer-demo
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```
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All ten demo window smoke tests need an active desktop session. Ordinary tests do not open windows.
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Run the additional file-backed ROM-window test explicitly in that desktop session:
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```sh
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direnv exec . cargo test --locked -p gameboy-rust-desktop --test rom_cli native_rom_window -- --ignored --test-threads=1
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direnv exec . cargo test --locked --release -p gameboy-rust-desktop --test rom_cli native_rom_window -- --ignored --test-threads=1
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```
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This opt-in test opens native windows in child processes and checks bounded presentation and STOP/CPU/video diagnostics.
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Each process has a host-side timeout. It does not require or validate physical keyboard presses.
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CPU-driven smoke tests supply scripted buttons; they do not validate physical keyboard events.
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To test the core and demo programs without building the window dependency:
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```sh
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direnv exec . cargo test --locked -p gba-core -p gba-demos
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```
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This excludes the desktop and command-line tests.
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The core's integration tests use `gba-demos` as a development dependency.
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On Apple Silicon, `file` must report a Mach-O `arm64` executable.
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Do not set a Linux cross-compilation target for this validation.
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The [headless ROM suite runner](rom-tests.md) provides explicit checkpoint and assertion results through `--test-suite PATH.json`.
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Its tests verify manifest limits, whole-suite validation, exact step boundaries, ARM/Thumb checkpoints, and register/CPSR/memory checks.
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Version 2 tests cover VBlank targets, initial/held/released input, captured RGB888 pixels, and render diagnostics.
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The original input ROM verifies CPU-observed button snapshots and every captured pixel without external game assets.
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Additional tests cover DMA/IRQ accounting, HALT/STOP, diagnostic state, case isolation, repeatable JSON output, and failure exit status.
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These original tests validate the runner. The [public ARM adapter](public-arm-tests.md) provides a separate passing checkpoint result for its pinned ROM.
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The [public Thumb adapter](public-thumb-tests.md) uses a separate lock and r7 assertion after its return to ARM state.
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The [public memory adapter](public-memory-tests.md) uses its own lock and an ARM-state r12 checkpoint.
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The [public BIOS adapter](public-bios-tests.md) also passes its ARM-state r12 checkpoint in debug and release builds.
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Preparation tests use only synthetic original bytes and no network:
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```sh
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direnv exec . python3 -B -m unittest discover -s tools -p 'test_*.py' -v
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```
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They verify suite selection, pinned URLs, hashes, sizes, checkpoint validation, offline copies, destination safety, and non-overwriting output.
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The [Pong adapter](public-pong.md) has additional offline tests for its pinned downloads, retained license, and bounded gameplay scenarios.
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Run the external Pong suite separately; ordinary Cargo and Python tests require no public ROM or network access.
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Device initialization regressions use original instructions to check disabled sound, wave RAM, disconnected serial pins, and reset flags.
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They verify explicit activation errors and atomic byte/word/block-store/DMA failure behavior.
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The optional [local Emerald startup check](research/emerald-reset.md) now reaches sound activation but still fails deliberately there.
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Thumb cases also verify the return-to-ARM bridge. Command-line tests cover default ARM selection, explicit Thumb/memory/BIOS selection, and errors.
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Compare/status CPU regressions verify saved flags/masks, bank switching, sequential PC/timing, User/System fallback, and atomic diagnostics.
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Load-alias regressions cover widths, signed/unaligned values, immediate/register offsets, pre/post-indexing, every non-PC register bank, and address wrapping.
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They verify loaded-value precedence, preserved flags, unchanged stores, nominal timing, I/O reads before device progress, deferred IRQ delivery, and atomic errors.
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ARM open-bus regressions cover unused-range boundaries, PC+8 source regions, byte lanes, signed/unaligned loads, writeback, and block loads.
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They check branch-target resampling, missing lookahead, skipped conditions, nominal timing, device progress, and retained host/fetch/DMA diagnostics.
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Thumb open-bus tests cover supported code regions, both instruction alignments, ROM windows, mirrors, and physical memory wrap.
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They check widths, sign extension, rotation, block/stack/PC loads, aliases, modes, state preservation, and sequential/branch resampling.
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Short-ROM tests require only the fetched halfword in 16-bit regions, including OAM-to-ROM boundaries.
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Mapped boundary tests cover palette/VRAM/OAM/ROM transitions, EWRAM-to-IWRAM lanes, and ROM page/wait-window crossings.
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They verify cold/retained pipelines, load widths and rotation, block/stack loads, split refills, rollback, and nominal timing.
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Unknown IWRAM lanes, missing ROM bytes, and unsupported I/O fetch values retain explicit diagnostics.
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See [fetch-region boundaries](research/fetch-region-boundaries.md) for source evidence and hardware-validation limits.
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Cold IWRAM tests now assert actual current/decode/lookahead lane updates before the first data read.
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Sequential IWRAM regressions check retained lanes across fetches, reads, writes, mirrors, and physical RAM wrap.
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They cover raw bus values before load rotation/sign extension, all modes, block transfers, and isolation from other memory regions.
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Known-bit tests reject incomplete words. Transaction tests verify discarded partial updates and preserved history after errors.
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Control-flow tests distinguish taken/untaken branches and refill Thumb IWRAM targets even when the target equals fallthrough.
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Refill tests cover ARM/Thumb BX, Thumb branches and BL, high-register PC writes, stack/block PC loads, and saved-state returns.
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They check both target alignments, mirrors/wrap, captured target+2 versus later target+4, widths, sign extension, and rotation.
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Original SWI/IRQ handlers verify return-time history. Failed returns, cold entry, region boundaries, DMA lane effects, and BIOS isolation retain checks.
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DMA tests compare source/destination lane updates against a byte-array reference, then apply the resumed PC+4 fetch.
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They cover channel preemption, blocked sources, failures, mirrors, pre-start lane establishment, cold fills, and other-region snapshot isolation.
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IRQ tests verify discarded-source lane updates and preservation across non-IWRAM fetches; PC discontinuities verify new pipeline-fill samples.
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Timed/untimed tests verify CPU results and nominal clock costs.
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Host/fetch isolation, separate BIOS history, unsupported stores/data regions, nominal device progression, and DMA diagnostics also have checks.
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ARM instruction-buffer tests verify retained P+4/P+8 words across CPU stores, DMA transfers, and host writes.
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They cover refill target pairs, PC writes to fallthrough, conditional branches, ARM/Thumb transitions, exception entry/return, and deferred fetch errors.
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Full CPU equality checks buffer and next-fetch-kind rollback and cloning.
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Successful instruction-semantic tests compare architectural state separately.
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Explicit invalidation tests cover debugger repair. Timed/untimed tests verify equal buffers without added nominal cycles.
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The display-runner error test allows an already buffered branch to complete before the patched unsupported word executes.
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Thumb instruction-buffer tests verify retained P+2/P+4 halfwords, BL prefix/suffix behavior, and state-tagged target pairs.
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They also cover stores, host/DMA writes, saved-state returns, deferred errors, mirrors, debugger repair, and nominal timing.
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Bus-history repair tests explicitly invalidate buffered code or repair a data address; failure checks retain full CPU equality.
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Debugger invalidation itself preserves local lanes, but the next cold fill drives current mapped instruction bytes.
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Persistent-latch tests cover ARM data accesses, ARM/Thumb target pairs, non-IWRAM code, IRQ handlers, and pre-start DMA.
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They also verify partial lanes and rollback of both cold-fill and resumed-instruction samples.
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Shared fetch-sample tests mutate memory between internal sampling and consumption to reject duplicate reads.
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They cover ARM words, Thumb narrow/wide buses, IWRAM lanes, target pairs, BIOS retention, and retry after failure.
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This test-only split is not a DMA scheduling feature. Separate tests verify strict fetch errors and no timing/history side effects.
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See [shared fetch samples](research/shared-fetch-samples.md) for the unchanged hardware limits.
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See [ARM instruction buffering](research/arm-instruction-buffer.md) and its [Thumb extension](research/thumb-instruction-buffer.md) for remaining limits.
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The pinned public ARM ROM now reaches its completion checkpoint with r12 = 0 in debug and release builds.
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The pinned public Thumb ROM also reaches its ARM-state checkpoint with r7 = 0 in both builds.
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Empty-list Thumb regressions cover PC+6, all low bases and processor modes, banked stacks, both code alignments, and unaligned data.
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They check one-word writes, 64-byte writeback, ROM windows, the following PC operand, nominal timing, and atomic errors.
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Existing ARM empty-list and Thumb empty-load tests continue to pass. `PUSH {lr}` retains its normal link value.
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The pinned public memory ROM also passes in both builds, but its video-byte assertions and mode selection have documented limits.
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Separate original CPU tests check exact video-byte results across supported modes, mirrored addresses, byte lanes, and boundaries.
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They require unchanged nonzero sentinels for ignored writes and unchanged adjacent halfwords for duplicated writes.
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They also check forced blank, full source-value preservation, CPU halfword readback, nominal data costs, and device progress.
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Halfword/word stores remain writable in object regions. No emulator behavior change was needed for these tests.
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These results do not establish full BIOS, timing, graphics, save, or commercial-game compatibility.
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ROM-runner tests use temporary files containing original instructions, without Nintendo assets or a desktop session.
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They check file-size boundaries, bounded reads, short reads, I/O errors, paths, symlinks, and read-only loading.
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CLI tests cover option order, missing/conflicting options, invalid step limits, process exit status, and reports.
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Execution tests cover original ARM/Thumb code, BIOS boot, DMA/IRQ step accounting, HALT budgets, and prompt STOP results.
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Unsupported instructions, truncated code, and DMA errors retain the failure state for inspection.
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ROM-window session tests compare every pixel from an original CPU-written palette with expected colors.
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They check keyboard-to-ROM input, focus loss, repeated STOP polling, keypad wake, HALT progress, and bounded slices.
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Further checks cover frame-budget retention/reset, DMA/IRQ step accounting, video errors, and final reports.
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See [cartridge execution](hardware/cartridge.md) for usage, limitations, and a generated original ROM for manual input testing.
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Angle-service tests compare results with wide-integer polynomial and signed-sector references, plus floating-point accuracy checks in supported ranges.
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They cover a dense ArcTan unit-interval grid, sampled full-domain and seeded inputs, axes, quadrant boundaries, signed extremes, and scale invariance.
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Other tests verify all caller flag combinations, User/System masks, non-result registers, stack bounds, repeated calls, diagnostics, and DMA/IRQ progress.
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Huffman tests use an independent tree serializer and path encoder, with expected output taken directly from original symbols.
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They cover every byte/nibble value, maximum tree size and offsets, deep paths across input-word boundaries, and seeded variable-length paths.
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Other tests check 24-bit byte lengths, malformed trees, output packing, truncation, partial failures, source regions, and DMA/IRQ behavior.
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Differential-filter tests round-trip original samples through an independent difference encoder, including all byte and halfword sample values.
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They cover seeded inputs, 24-bit byte lengths, full-register accumulation wrap, output widths, source regions, and caller status.
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Malformed headers, truncated inputs, partial output, video-bus behavior, DMA progress, and masked IRQ delivery have separate regression tests.
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BitUnPack tests compare all supported width pairs and byte values with an independent bit-by-bit reference.
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They cover offsets and the zero-data flag, seeded inputs, maximum source length, source alignment, and ROM descriptors.
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Other tests check output boundaries, video-memory word writes, malformed/truncated inputs, partial failures, caller status, and DMA/IRQ behavior.
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Run-length tests cover all 256 block-control values and repeated byte values, plus seeded mixed streams and 65,536-byte output.
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They verify ARM/Thumb callers, User/System status restoration, stack bounds, source regions, and exact output boundaries.
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Other tests check malformed/truncated input, halfword buffering, normal video-bus writes, DMA progress, and masked IRQ delivery.
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Sprite allowance tests cover regular/affine costs, doubled canvases, partial prefixes, inactive inspection, clipping policy, and OAM-order allocation.
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They check transparent, occluded, out-of-texture, and bitmap-restricted work, plus independent row allowances and preserved diagnostics.
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DISPCNT bit5 boundary writes and HBlank DMA verify preparation-time sampling. Static captures match immediate snapshots.
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Budget unit tests compare every allowance and supported canvas width with independent cycle consumption, plus seeded mixed workloads.
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Sprite preparation tests check cycle39/40/41 boundaries, buffered attributes and indices, late palette/effect lookup, and affine matrices.
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They cover OBJ windows, horizontal mosaic, global enable, forced blank, HBlank DMA, row0 preparation, and deferred diagnostic recovery.
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Large capture-disabled batches and capture toggles preserve prepared rows. Failed CPU steps and zero-cycle advances do not prepare rows.
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An independent line-event model checks preparation scheduling, including maximum-length clock batches.
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Horizontal window tests cover all 65,536 bound combinations, partial-cycle boundaries, missed edges, and right-edge precedence.
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They compare random register/clock sequences with independent dot iteration and check maximum-length batches.
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Integration tests cover hidden columns, late HBlank DMA, independent windows, CPU stores crossing edges, and capture independence.
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They also preserve the distinction between window history and row-sampled pixel colors.
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Vertical mosaic tests cover size growth, size shrinkage, four-bit wraparound, byte writes, independent counters, and frame resets.
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They check affine origin updates, sprite partial blocks, OBJ-window exclusion, live memory sampling, DMA ordering, and capture independence.
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All counter values and heights are compared with independent iteration across every visible line interval.
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Random clock batches, maximum-length batches, and failed-write atomicity also have regression coverage.
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Vertical window tests cover missed edges, equal bounds, hidden rows, frame wrap, byte/word writes, and independent WIN0/WIN1 state.
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They check DMA ordering, enable/forced-blank behavior, snapshot independence, capture toggles, and failed-write atomicity.
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All 65,536 vertical bound combinations are checked against an independent edge-iteration model across two frames.
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Additional tests compare random clock batches and a maximum-length batch against individual line transitions.
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Affine tracking tests cover cumulative coefficients, partial reference writes, per-axis reloads, mode/enable gates, and frame reloads.
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They also check mosaic blocks, window masking, forced blank, capture-independent tracking, and failed-write atomicity.
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A deterministic 500-case test compares batched affine tracking with an independent line-boundary model.
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The affine raster demo tests verify DMA tables, all rotation/zoom/bypass combinations, negative panning, reset, and every pixel.
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Capture tests cover exact HBlank/VBlank boundaries, partial startup frames, repeated enable, disable, large batches, and zero-cycle advances.
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They check immutable completed images, deferred rendering errors, recovery, and equivalence with single-cycle clock advancement.
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Mid-frame tests change palettes, video RAM, OAM, bitmap pages, scroll, windows, mosaic, brightness, forced blank, and green swap.
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Static captures match snapshots across all six modes with sprites and effects.
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Machine tests check HBlank/VBlank DMA ordering, HALT progress, VCOUNT polling, failed instructions, and the instruction-boundary timing policy.
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The CPU raster demo tests verify table copying, DMA rearming, phase wrapping, opposite keys, reset, and every displayed pixel.
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Mosaic tests cover every dimension, both bitmap pages, text flips and scrolling, affine transforms, transparency, and independent enable flags.
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Sprite tests check screen-aligned blocks, partial first blocks, wrapping, regular/affine sampling, and double-size drawing areas.
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They also check horizontal latch transitions, transparent priority updates, unchanged OBJ-window coverage, window edges, and alpha blending.
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CPU tests cover all sixteen sizes, size cycling, scrolling, rotation/zoom, independent bypass controls, reset, and DMA writes.
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Window tests cover bounds, wrapping, overlap precedence, layer masks, effect gating, OBJ coverage, and regular/affine window sprites.
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Color tests cover five-bit rounding, saturation, coefficient clamping, backdrop selection, immediate targets, and semi-transparent OBJ precedence.
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They check all display modes, green swap, forced blank, register widths, DMA writes, and CPU-driven brightness frames.
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The native effects smoke test verifies every pixel across brightness increase, decrease, alpha blending, and window movement.
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A CPU-demo regression checks retained vertical state when the moving bottom reaches the unreachable bound228.
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Mode 4/5 tests cover both page boundaries, byte ordering, hidden-page writes, palette changes, transparency, and opaque black.
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They check source dimensions, affine transforms against wide-integer references, clipping, sprite restrictions, and memory write rules.
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Both CPU bitmap demos run across two automatic page transitions. Tests compare every displayed pixel and verify VBlank synchronization.
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Additional tests cover panning, rotation, zoom, forced page selection, opposite directions, and reset.
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Affine background tests compare all map sizes and both backgrounds against a separate wide-integer sampling reference.
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They cover signed origins, reference masking, register access widths, clipping, wrapping, tile255, and character base3.
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Other tests cover Mode 1 text/affine mixing, independent BG2/BG3 state, priorities, sprites, and Mode 3 transforms.
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The CPU background demo test checks negative panning, opposite keys, reset, every control combination, and every output pixel.
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Snapshot tests verify the debug API's whole-frame register policy. Capture tests separately verify the documented HBlank row-sampling policy.
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Affine tests compare identity matrices against regular sprites across every shape, size, color depth, and tile layout.
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A separate floating-point reference checks rotation, reflection, shear, fractional scaling, negative rounding, and double-size drawing areas.
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Tests also cover all 32 matrix groups, shared matrices, coordinate wrapping, singular/extreme values, priorities, and bitmap tile restrictions.
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The CPU demo test checks all Q/W/Z/X combinations, matrix writes, preserved screen center, and return to regular mode.
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Sprite tests cover OAM mirrors, ignored byte writes, DMA transfers, every shape/size, and both palette depths.
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They check 1D/2D layouts, address wrapping, odd eight-bit bases, flips, clipping, opaque black, and priority selection.
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Other tests check Mode 3 tile restrictions, green swap, disabled objects, and unchanged output after diagnostics.
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The CPU demo test checks sprite controls, OAM attributes, disabled unused objects, and every output pixel.
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Tile tests cover both color depths, palette banks, flips, all map sizes, scrolling, transparency, priorities, and register masks.
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They check errors for unsupported features and out-of-range fetches without changing the output image.
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The CPU tile demo test verifies asset copies, every pixel, wrapping, opposite directions, reset, and VBlank synchronization.
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RegisterRamReset tests check full memory regions and all memory-flag combinations from ARM and Thumb.
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They verify forced blank, reserved flag bits, caller preservation, protected BIOS RAM, and selective serial/sound initialization.
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All-device reset returns from ARM and Thumb; active sound and serial operations remain separately tested diagnostics.
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Rendering tests check write-only display state, both identity matrices, and the effect of zeroed sprite attributes.
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Device tests check DMA address/count latches, stopped timer counters, cleared reloads, and IRQ acknowledgement.
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Other checks cover partial clears, preserved input/device state, and callers whose own RAM code is erased.
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SoftReset tests check every restart flag byte from ARM and Thumb, exact RAM clearing, and preserved memory.
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They seed CPU banks and verify stack pointers, link registers, saved status, caller modes, and restart status.
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Other tests execute RAM restart code, call BIOS services again, and restart from code inside the erased region.
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Device tests check retained I/O state, advancing timers/DMA, pending IRQs, and instruction-by-instruction RAM clearing.
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BIOS affine tests check all 256 angle phases against independent trigonometric and wide-integer references.
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They cover signed scales, origin wraparound, rounding, ignored angle bits, strides, alignment, and partial failures.
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Live rendering tests apply generated matrices to background registers and sprite attribute memory.
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Other checks cover ARM/Thumb calls, register/status preservation, stack bounds, DMA, timers, and deferred IRQ delivery.
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Image-builder tests verify multiple literal pools, branch fixups, and reserved table boundaries.
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BIOS arithmetic tests cover signed boundaries, division overflow/zero, all sign combinations, and seeded integer inputs.
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Square-root tests check exact integer bounds around perfect squares and across unsigned inputs.
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LZ77 tests compare emitted-code execution against independent token expansion, including 4,096-byte distances and overlapping runs.
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They also check byte/halfword output, exact buffer boundaries, stack limits, malformed headers/references, and truncated input.
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BIOS tests cover ARM/Thumb service decoding, register/status restoration, default stacks, unsupported calls, and IRQ dispatch.
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Copy tests cover widths, fill, zero count, reserved bits, alignment, overlap, FastSet rounding, protected sources, and partial failures.
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Wait tests inject an IRQ at 100 different machine-step positions to check the flag-check/HALT transition.
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Other wait tests cover discarded flags, unrelated IRQs, masked/User-mode callers, and callbacks that omit BIOS flag updates.
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HALT tests distinguish wake-up from IRQ delivery, including IME/CPSR masking and ARM/Thumb resume behavior.
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Idle batches are checked against a cycle-by-cycle reference with independent and cascaded timers.
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Tests cover display/DMA wake sources, DMA priority while halted, BIOS-only writes, power-state validation, and frame limits.
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STOP tests check zero-cycle idle steps, frozen DMA/timers/display, retained timer phases and captured frames, and live keypad wake.
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They distinguish wake-up from IF latching and test stale requests, interrupt masks, already-held keys, and normal resume ordering.
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ARM/Thumb BIOS Stop tests verify caller preservation. Frame-runner tests check prompt stopped results and unchanged output images.
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The graphics test verifies BIOS VBlank waiting, one IRQ callback per update, and status restoration before each redraw.
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DMA tests cover both widths, all supported address modes, count limits, register masks, enable latches, and repeated transfers.
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Original channel-data tests cover word retention, halfword duplication, blocked-source destination lanes, and channel isolation.
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They check cold/zero history, cancel/re-enable, source-counter crossings, repeats, priority, failed-unit rollback, and BIOS snapshot isolation.
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These tests do not establish general DMA open-bus reads or DMA-to-CPU handoff. See [the research scope](research/dma-data-latches.md).
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Tests verify channel priority/preemption, CPU pausing, display/timer progress, IRQ acknowledgement/return, and WAITCNT costs.
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CPU resume tests cover ARM/Thumb widths, all ROM-window wait settings, one-shot N timing, and RAM-only DMA.
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They check errors, host isolation, mixed timed/untimed APIs, WAITCNT updates, refills, IRQ entry, HALT/STOP, and timer delivery.
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These verify the [nominal resume subset](research/dma-resume-timing.md), not a full fetch pipeline or physical-hardware timing.
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Diagnostic tests check failed-unit isolation, retained earlier transfers, unsupported modes, and CPU block-store atomicity.
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Graphics startup tests verify that DMA3, not CPU stores or host writes, fills every background pixel.
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Display tests cover exact scanline boundaries, line-227 VBlank behavior, all 228 HBlank events, and read-only status fields.
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Bulk display advancement is checked against a cycle-by-cycle reference, including invalid comparison values and large batches.
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Original IRQ-handler tests cover VBlank, HBlank, and VCount-match delivery, acknowledgement, and return.
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Frame tests verify consecutive VBlank events, step limits, error handling, and independence from the demo's RAM counter.
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Graphics tests check CPU-generated pixels, movement, edge clamping, opposite directions, colors, and reset behavior.
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Video tests cover mirrors, byte-write rules, RGB555 layout, backdrop, forced blank, green swap, and unsupported modes.
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Input tests cover all 1,024 button combinations, read-only KEYINPUT behavior, keyboard mapping, and focus loss.
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Keypad tests compare every button-state/selection pair with independent per-button OR/AND logic.
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They check all KEYCNT values, byte merging, complete-word sampling, empty masks, and repeated request behavior.
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Integration tests cover CPU/DMA writes, interrupt masks, HALT wake-up, ARM/Thumb IRQ return, and original BIOS IntrWait.
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Failed-store tests check register, IRQ-history, CPU, and clock preservation. BIOS reset tests verify retained KEYCNT state.
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The bounded graphics frame runner is checked for instruction errors and timeouts.
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Timing tests cover every ROM wait-state setting, access width, ROM window, and 128 KiB boundary handling.
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Fetch-address regressions place executing instructions before memory-region and ROM page/wait-window boundaries.
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They check ARM/Thumb widths, cold/retained pipelines, independent N/S tables, DMA resume, and pre-write WAITCNT settings.
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Other checks cover deferred fetch errors, source-plus-target refill totals, timer advancement, and subsequent IRQ sampling.
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Startup-ROM and timer expectations now use P+8/P+4 rather than the executing address; data and rollback assertions remain intact.
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See [fetch-address timing](research/fetch-address-timing.md) for the bounded scope.
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Refill timing tests cover incoming/outgoing widths, all ROM wait settings, and target first/second/third-slot page boundaries.
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They verify source DMA overrides, split wait-window pairs, missing source/target diagnostics, masked IRQ isolation, and device totals.
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IRQ history tests verify word/halfword lane updates without invented cold fills or BIOS instruction snapshots.
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See [refill timing](research/refill-fetch-timing.md) for source evidence and public-report changes.
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Instruction-pair tests cover following-fetch kinds after transfers, swaps, register shifts, multiplies, status operations, and skipped conditions.
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They use independent N/S tables across every ROM window and wait setting, including settings where N is cheaper than S.
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They check timed/untimed equivalence, clones, IRQ/DMA composition, repeated transfers, PC-load refills, failed steps, and cold-start policy.
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Page/wait-window crossings, masked IRQs, host/HALT isolation, and pre-write WAITCNT settings retain separate checks.
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See [persistent fetch access kinds](research/fetch-access-sequencing.md) for evidence and public-report changes.
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Timing-event tests inspect source/data/internal/refill order and metadata independently of aggregate cycle costs.
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They cover the full LDM register list, PC loads, Thumb POP, state changes, skipped branches, swaps, shifts, and IRQ entry.
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WAITCNT snapshots, late failure rollback, deferred fetch errors, and host/DMA isolation have separate checks.
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CPU-only execution joins the timing path when prefetch is enabled.
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Test-only event logs do not add a production allocation or a public trace API.
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Prefetch queue tests cover every ROM wait setting and width, partial ARM words, full-buffer stops, restart, and cancellation phases.
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They also check page/window boundaries, configuration changes, and batched-versus-single-clock consistency.
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Integration tests check RAM/internal progress, ROM data stalls, branch and IRQ fetches, CPU-only equivalence, and debugger invalidation.
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WAITCNT CPU/host/DMA writes, RAM/cart DMA, HALT/STOP, failed steps, and missing ROM bytes have separate checks.
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See [prefetch evidence and limits](research/gamepak-prefetch.md). These tests validate the nominal model, not physical-hardware accuracy.
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An [original cancellation probe](research/prefetch-cancellation.md) compares read/control intervals with pinned, published hardware observations.
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Both its instruction-boundary totals and actual timer samples now match. Any mismatch still returns a nonzero status.
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Regressions retain the original program and published observations without correcting the loaded timer values.
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Disabled-prefetch controls, delay bounds, completion PCs, and fresh-run determinism have separate checks.
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Instruction timing tests cover arithmetic, shifts, branches, transfers, block operations, multiply, and exception returns.
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Timed and untimed execution are compared across all 65,536 Thumb encodings with fixed initial registers.
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Timer/IRQ tests verify that changing WAITCNT changes when an interrupt is sampled.
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Timer tests cover all prescalers, reload changes, start/stop behavior, byte writes, large clock advances, and cascades.
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Ordered timer tests cover ARM/Thumb sampling, coherent byte lanes, block-transfer phases, reload/control ordering, and prescaler retention.
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They verify timer IF reads/acknowledgements, preservation of other IF bits, deferred IRQ delivery, DMA phases, and HALT/STOP ownership.
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Failures before fetch and after partial data work must discard staged time and requests. CPU-only APIs must not advance timer devices.
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Display-capture splits must not tick committed timers a second time. See [ordered timer accesses](research/ordered-timer-access.md).
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Bulk timer advancement is compared against an independent cycle-by-cycle reference for each prescaler and cascade configuration.
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Shared-divider tests cover every low-ten-bit phase, staggered enables, source changes, restarts, and cascade transitions.
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A separate literal edge simulation checks randomized control/reload/clock sequences without a per-timer phase accumulator.
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Maximum clock batches, HALT bounds, STOP/keypad retention, and CPU/DMA rollback across divider edges have original regressions.
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See [shared timer prescaler scope](research/timer-prescaler.md); delayed write and startup behavior remains unverified.
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Machine tests cover ARM/Thumb IRQ return, pending-request gating, acknowledgement, and the complete timer demo.
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Failed I/O block transfers are checked for partial register writes, hidden reload changes, and unintended IF acknowledgement.
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Status tests cover all modes, flag combinations, interrupt masks, field selection, privilege rules, and bank isolation.
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Exception tests cover vectors, ARM/Thumb return addresses, nested interrupts, mask priority, and return-state restoration.
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User-bank transfers and failed returns are checked for unintended changes to active and hidden registers.
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Integration tests execute original vector handlers and check optional BIOS mapping boundaries and write protection.
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Original BIOS-access regressions check retained ARM PC+8 and aligned Thumb PC+4 words for ARM/Thumb callers.
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They cover all processor modes, load widths, lanes, rotation, both Thumb code alignments, and distinct halfwords.
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They verify direct reads while executing inside BIOS, re-entry, SWI/IRQ returns, host-inspection isolation, and original-boot provenance.
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Thumb tests cover sequential snapshots, instruction-state transitions, SWI entry, and RAM-backed POP exits.
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Unknown history, last valid fetch words, missing lookahead, and diagnostic-step retention have explicit checks.
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Unknown IWRAM lanes remain diagnostic until observed accesses establish them; mapped cold pipeline fills now establish both halves.
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Separate tests cover sequential/refill history, general Thumb snapshots, and retained BIOS history.
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Protected loads keep normal nominal costs and advance devices only through machine stepping.
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Firmware readback regressions separately verify documented boot, SoftReset, returning SWI, IRQ callback, and IRQ return words.
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They execute ARM/Thumb loads across widths and lanes, check caller state, and trace actual exits to their image data.
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Interrupt waits replace callback readback with SWI readback on return. Builder tests check branch/literal relocation around exit data.
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A modified original image verifies that the bus retains supplied data rather than forcing compatibility constants.
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The pinned public BIOS ROM passes unchanged; this is a bounded protected-read result, not complete BIOS conformance.
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Display tests cover color conversion, framebuffer bounds, cursor movement, pause behavior, and animation wraparound.
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Input regression tests check focused arrow keys, focused Space presses, and ignored input when unfocused.
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Command-line tests cover mode selection and invalid arguments.
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Condition tests cover all 15 defined conditions against all 16 flag combinations.
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Arithmetic tests check all 4,096 immediate encodings against nine boundary operands for `ADDS`, `SUBS`, and `CMP`.
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Arithmetic-with-carry tests use wider signed and unsigned integers as an independent reference.
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Shifter tests compare all 256 register-shift amounts against a bit-at-a-time reference.
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Instruction tests cover all data-processing opcodes, addressing modes, PC offsets, signed loads, and multiply.
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Block-transfer tests cover all four addressing modes, base-register overlap, empty lists, alignment, and failure handling.
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Swap tests cover byte and word transfers, register aliases, and failed writes to cartridge ROM.
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Thumb tests cover arithmetic, memory, stack operations, branch offsets, high registers, and ARM/Thumb switching.
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The decoder test steps all 65,536 Thumb encodings with fixed initial registers and checks for panics or partial CPU changes on errors.
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This decoder test checks robustness, not hardware compatibility for every encoding or register value.
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Other tests check flag preservation, skipped instructions, memory errors, and the complete mixed ARM/Thumb demo.
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These tests do not replace validation against GBA hardware or public hardware test programs.
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