663b25e5d1
Update existing Thumb IWRAM continuation lanes from successful DMA reads and writes before the resumed PC+4 snapshot. Keep channel halfword duplication separate from actual lane accesses. Preserve atomic errors, cold-entry diagnostics, IRQ invalidation, and nominal timing. Add original DMA matrices and resume regressions; update prior invalidation expectations. Record pinned ares and jgenesis evidence and explicit limits for cross-state history, general open bus, and sub-instruction arbitration. Validated on Darwin arm64: 939 workspace and 870 core/demo tests per debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports remain identical to the previous results.
76 lines
5.6 KiB
Markdown
76 lines
5.6 KiB
Markdown
# DMA retained data and CPU bus ownership
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## Finding
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DMA channel data, IWRAM lane history, and the CPU's general bus value are different state.
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A channel's retained data cannot safely replace every open-bus read after a transfer.
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The previous implementation rejected all DMA sources below work RAM, even after the channel had transferred known data.
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That diagnostic omitted a documented retained-data case.
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The [NanoBoyAdvance hardware latch test](https://codeberg.org/nba-emu/hw-test/src/commit/cc3f4a286cdef823980d9b353bd70befc9927d28/dma/latch/source/main.c) specifies these expectations:
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- Each DMA channel retains its own 32-bit value.
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- A mapped word source replaces that value.
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- A mapped halfword source duplicates its value in both retained halfwords.
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- A blocked BIOS source does not replace the retained value.
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- A halfword write from a blocked source selects the retained lane using destination bit 1.
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- A write-only I/O source can read ordinary bus history, not simply the previous channel value.
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The test explicitly exercises source zero. Its comments extend the blocked-source rule below `0x02000000`.
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[NanoBoyAdvance's DMA implementation](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/hw/dma/dma.cc) and [ares DMA](https://github.com/ares-emulator/ares/blob/6f6786e04f0822a3475463df284f313ab8518d51/ares/gba/cpu/dma.cpp) use that boundary.
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Both retain channel data across transfers and duplicate successful halfword reads.
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These sources support the implemented subset, but do not establish cold hardware latch contents.
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## Why CPU resume remains separate
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[NanoBoyAdvance's bus](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/bus/bus.cc) tracks the last access type.
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Its open-bus path can select DMA data when DMA was the preceding access.
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DMA runs within CPU bus calls, so that condition depends on which CPU access resumes.
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It does not imply that every first instruction after DMA must return a channel value.
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[ares bus dispatch](https://github.com/ares-emulator/ares/blob/6f6786e04f0822a3475463df284f313ab8518d51/ares/gba/cpu/bus.cpp) routes DMA accesses through the relevant memory buses.
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Its IWRAM bus and general data register are separate, and pending DMA runs before CPU accesses.
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GBATEK's possible DMA influence on IWRAM is not sufficient to choose CPU resume ordering here.
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Our instruction-boundary scheduler does not yet represent these per-access transitions.
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The initial channel-latch change kept successful-DMA invalidation of bounded Thumb IWRAM history.
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The later [DMA continuation extension](iwram-bus-history.md#dma-continuation-extension) models local IWRAM lanes at instruction boundaries.
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Failed DMA preserves that history. No universal channel-value override is injected into CPU or BIOS snapshots.
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General CPU-bus work still needs independent resume-ordering coverage rather than a universal last-transfer override.
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## Implemented subset
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Each `dma::Channel` holds `Option<u32>` retained data. `None` means synthetic startup has not established a value.
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A pending `Transfer` includes that channel's value, but selection does not change it.
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`Memory::step_dma` validates the destination and obtains either mapped source data or known blocked-source data.
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For mapped halfword sources, both retained lanes receive the source halfword.
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For blocked sources, the retained word stays unchanged and the destination selects the written halfword.
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No BIOS image read occurs in the blocked path.
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After a successful write and nominal device progress, completion commits the retained word with the unit's existing address/count changes.
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Enable, disable, cancellation, completion, and repeat do not clear retained data.
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Each channel remains independent. Host operations and CPU reads never seed channel data.
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Unknown blocked sources retain `DmaError::UnsupportedSource`; known zero is valid data.
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Other unmapped sources and unsupported controls remain diagnostics even with known channel data.
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The existing atomic diagnostic policy commits no new latch value for a failed unit.
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Earlier successful units remain visible. A partial failed read cannot replace their retained value.
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Nominal source/destination costs, CPU pausing, trigger scheduling, and completion IRQs are unchanged.
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General DMA open-bus reads, write-only register readback, and general CPU resume ownership remain outside this subset.
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Local IWRAM lane effects are now covered by the separately bounded continuation extension linked above.
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## Validation scope
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Original regressions cover both widths, all channels, source/destination halfword lanes, and supplied or absent BIOS images.
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They check independent ownership, zero/unknown values, host isolation, source-counter crossings, cancellation, repeats, priority, and failed-unit retention.
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A CPU instruction sequence also checks that blocked DMA leaves the separately retained BIOS word unchanged.
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The new retained-data cases failed on the previous unconditional blocked-source diagnostic.
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External source and license files were reviewed outside the repository.
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No external test ROM or source was imported. The hardware latch ROM was not built or run here.
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These are original regression checks, not a local physical-hardware or external-emulator differential result.
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Workspace and core/demo tests pass on Darwin arm64 in debug and release builds.
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Formatting, lint checks, rustdoc, preparation tests, native ROM windows, and all graphics smoke modes pass.
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Public ARM, Thumb, memory, and BIOS reports match the previous passing reports exactly.
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Those suites are regression checks, not independent validation of retained DMA data or CPU bus handoff.
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