49 lines
3.1 KiB
Markdown
49 lines
3.1 KiB
Markdown
# Sound initialization subset
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Sound synthesis and host audio output are not implemented.
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The core now models disabled sound-register state so firmware can perform a functional sound reset.
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This is not a silent-audio compatibility mode. Enabling sound returns an explicit diagnostic.
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## Supported state
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| Address | Behavior |
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| --- | --- |
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| `0x04000060..0x04000081` | Programmable sound generator (PSG) registers remain zero; writes have no effect while master sound is disabled |
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| `0x04000082` (`SOUNDCNT_H`) | Retains mixing/routing/timer configuration with readback mask `0x770f` |
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| `0x04000084` (`SOUNDCNT_X`) | Reads zero; status flags are read-only; a write setting bit 7 fails |
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| `0x04000088` (`SOUNDBIAS`) | Retains bias/resolution configuration with mask `0xc3fe`; no analog output is generated |
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| `0x04000090..0x0400009f` | Read/write wave RAM in the CPU-accessible inactive bank |
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Unused mapped bytes through `0x0400008b` read zero and ignore writes.
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The FIFO reset strobes in `SOUNDCNT_H` do not latch. No FIFO data can be queued in this subset.
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FIFO addresses and the remaining sound-region holes stay unmapped.
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All sound configuration starts at zero in raw memory. RegisterRamReset bit 6 sets the functional bias default to `0x0200`.
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With master sound disabled, `SOUND3CNT_L` stays zero. The CPU accesses wave bank 1.
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Bank 0 cannot be selected or played and remains zero. Disabling master sound does not erase wave RAM.
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The BIOS reset explicitly clears the accessible wave RAM through ordinary stores.
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Future bank switching and channel playback need a complete sound engine, not a larger register array.
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## Diagnostics and atomicity
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A write setting `SOUNDCNT_X` bit 7 returns `MemoryError::UnsupportedIo`, including the address, byte value, and operation.
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Status bits and unused bits alone do not enable sound.
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Validation occurs before any bytes in the access are written.
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Block stores validate every register value before committing earlier writes. Failed CPU and DMA steps remain retryable.
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Original tests cover disabled-register writes, masks, byte lanes, wave retention, and BIOS reset selection.
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They also check rejected sound activation through byte/word accesses, ARM block stores, and DMA without partial state changes.
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## Remaining work
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Implement channel clocks, length/envelope/sweep state, wave banking, FIFO consumption, timer-triggered sound DMA, and mixing.
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Add a host-independent sample interface before connecting a desktop audio backend.
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Do not acknowledge active sound requests without implementing their device behavior.
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## References
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- [GBATEK sound control registers](https://problemkaputt.de/gbatek-gba-sound-control-registers.htm): disabled PSG behavior, master enable, masks, FIFO reset strobes, and bias.
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- [GBATEK](https://mgba-emu.github.io/gbatek/): channel 3 wave-bank access and register layout.
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- [mGBA BIOS service implementation at 3a5e34be](https://github.com/mgba-emu/mgba/blob/3a5e34be33dc7f8f707e5bc9db69e8a430046f21/src/gba/bios.c): functional reset defaults. No upstream implementation was copied.
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Reset values are source-backed. Exact Nintendo firmware ordering, timing, and analog behavior are not established.
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