43 lines
3.1 KiB
Markdown
43 lines
3.1 KiB
Markdown
# Disconnected serial initialization subset
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The core supports idle normal-mode data registers and disconnected general-purpose pins.
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It does not support link transfers, multiplayer, UART, Joybus communication, or external serial interrupts.
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Unsupported activity remains diagnostic rather than reporting a fabricated completion.
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## Registers
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- `SIODATA32` at `0x04000120` is a four-byte latch in the supported normal-mode subset.
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- `SIODATA8` at `0x0400012a` retains its low byte; its upper byte reads zero.
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- `SIOCNT` at `0x04000128` retains normal 8/32-bit mode, IRQ configuration, clock selection, and the output-data bit.
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The retained mask is `0x500b`. The disconnected serial input is high, except when a general-purpose output drives it low.
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Transfer-start bit 7 and multiplayer/UART mode bit 13 return explicit errors.
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- `RCNT` at `0x04000134` retains general-purpose mode, output latches, and pin directions with mask `0x80ff`.
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In general-purpose mode, each input reads high through its pull-up. Each output reads its output latch.
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`RCNT=0x8000` therefore reads back as `0x800f`, not `0x8000`.
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Joybus mode and GPIO interrupt enable return errors. Normal-mode low-byte pin readback remains unmapped rather than guessed.
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- `JOYCNT` permits clearing already-empty status flags. Joybus interrupt enable is unsupported.
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- `JOY_RECV` and `JOY_TRANS` permit only zero writes and zero readback for reset initialization.
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Nonzero writes return an explicit error. Joybus status and data-transfer side effects are not implemented.
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GPIO means general-purpose input/output. UART means universal asynchronous receiver/transmitter.
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No external serial device is connected. Elapsed cycles alone do not change serial data or generate an IRQ.
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Configuration that hardware accepts in other modes can still be rejected by this intentionally limited subset.
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## BIOS reset
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RegisterRamReset always clears the low halfword of SIODATA32, even without bit 5.
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The upper halfword remains unchanged in this functional subset.
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With bit 5 selected, the firmware clears SIOCNT and SIODATA8, selects general-purpose inputs, and clears the supported Joybus reset registers.
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It uses ordinary ARM bus stores, not a host-side reset bypass.
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Original tests cover independent byte lanes, input pull-ups, output directions, reset flag selection, and explicit unsupported operations.
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Whole-access and block-store validation prevent a rejected control value from committing preceding bytes or registers.
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## References
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- [GBATEK reset functions](https://problemkaputt.de/gbatek-bios-reset-functions.htm): reset flags, general-purpose selection, and the unconditional SIODATA32 side effect.
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- [GBATEK normal serial mode](https://problemkaputt.de/gbatek-sio-normal-mode.htm): data widths, input status, and control bits.
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- [GBATEK](https://mgba-emu.github.io/gbatek/): general-purpose pin directions and internal pull-ups.
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- [mGBA BIOS implementation at 3a5e34be](https://github.com/mgba-emu/mgba/blob/3a5e34be33dc7f8f707e5bc9db69e8a430046f21/src/gba/bios.c): functional serial reset defaults, not copied source.
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Exact firmware write ordering and hardware pin timing remain unverified.
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