16286e0cbd
Retain one pending non-sequential resume after successful DMA. Apply it to the next nominal non-refill code access and consume it only on successful CPU or IRQ progress. Preserve failed-step atomicity, host and idle isolation, existing refill costs, and WAITCNT ordering. Add 13 original regressions for ARM/Thumb widths, ROM wait settings, sources, preemption, retries, mixed APIs, idle states, and interrupt timing. Record pinned hardware-test source and emulator evidence without claiming physical-hardware or full-pipeline conformance. Validated on Darwin arm64: 952 workspace and 883 core/demo tests per debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports remain unchanged.
74 lines
5.2 KiB
Markdown
74 lines
5.2 KiB
Markdown
# Non-sequential CPU resume after DMA
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## Finding and evidence
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DMA can break the CPU's sequential bus access even when the transfer uses only work RAM.
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The prior instruction timing path always used its instruction summary, without retaining DMA ownership changes.
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An ordinary ROM instruction after DMA therefore still received a sequential code-access cost.
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Sources reviewed:
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- [NanoBoyAdvance force-nseq-access test at cc3f4a28](https://codeberg.org/nba-emu/hw-test/src/commit/cc3f4a286cdef823980d9b353bd70befc9927d28/dma/force-nseq-access/source/main.c) compares EWRAM-source and ROM-source transfers during a short instruction sequence.
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Both tests specify the same timer result. This is a whole-sequence expectation, not an isolated first-fetch measurement.
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- [NanoBoyAdvance bus at 55b5cf0a](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/bus/bus.cc) forces non-sequential ROM access when the previous access was DMA and the current access is CPU.
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The condition does not require the DMA source or destination to be ROM.
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- [ares DMA at 6f6786e0](https://github.com/ares-emulator/ares/blob/6f6786e04f0822a3475463df284f313ab8518d51/ares/gba/cpu/dma.cpp) marks ARM7 accesses non-sequential when DMA takes bus ownership.
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Its [bus dispatch](https://github.com/ares-emulator/ares/blob/6f6786e04f0822a3475463df284f313ab8518d51/ares/gba/cpu/bus.cpp) uses that state for CPU burst selection.
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These sources support a sequence break. They do not establish exact timing for our instruction-boundary scheduler.
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The public test source was reviewed outside the repository. Its ROM was not imported, built, or executed here.
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No physical-hardware measurement or external-emulator differential run was performed.
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## Bounded implementation
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A successful DMA unit sets a pending non-sequential CPU resume in `Memory`.
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Further units and channel changes keep that single pending state. They do not queue additional costs.
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A failed unit cannot create or consume it. A blocked-source unit that successfully writes known channel data sets it normally.
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Register configuration, host reads/writes, and clock-only advancement do not consume it.
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Before instruction execution, `Cpu::step_timed` captures the pending state and WAITCNT.
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For a non-refill instruction, pending resume changes the nominal code-access kind to non-sequential.
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The existing bus-cost function applies the code width and ROM-window wait settings.
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An ARM word still uses a non-sequential first halfword and a sequential second halfword.
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This is a change of access kind, not a fixed positive surcharge: some wait settings make N cheaper than S.
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Successful CPU execution consumes the pending state in timed and untimed APIs.
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Skipped conditions consume it too. Failed fetches, unsupported instructions, and failed data accesses preserve it for retry.
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Execution in internal memory consumes it even when N and S costs are equal.
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The state does not wait for a later ROM instruction.
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Machine IRQ entry consumes it through successful CPU-step completion.
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HALT/STOP idle does not consume it. Normal device progress, wake-up, and IRQ sampling rules still apply.
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A CPU WAITCNT store uses the pre-instruction settings for its code access.
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A completed DMA WAITCNT store changes the settings before CPU resume.
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## Limits
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The model has no persistent fetch pipeline or per-access DMA arbitration.
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It charges the current instruction address, not a separately scheduled PC+4/PC+8 pipeline fetch.
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DMA still executes only between instructions, not between data accesses or during CPU internal cycles.
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Existing refill summaries remain destination-based `1N+2S` costs.
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A resumed branch or exception consumes pending state without adding another nominal access.
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This prevents double-counting the existing N component, but does not model the discarded old-PC fetch separately.
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Stores and 128 KiB ROM boundaries already use N and receive no duplicate cost.
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Game Pak prefetch remains unimplemented; WAITCNT bit 14 does not alter this nominal timing path.
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This change does not select a DMA value for CPU open-bus reads.
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DMA channel data, bounded IWRAM lane history, and protected BIOS history remain separate.
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General bus-data ownership and exact resume timing still need independent per-access validation.
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## Original regression coverage
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Tests cover ARM/Thumb widths, all three ROM windows, every N/S wait setting, and stored prefetch-bit values.
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They check RAM/ROM DMA sources, repeated units, channel preemption, blocked-source completion, and configuration-only isolation.
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Other checks cover CPU/DMA errors, mixed timed/untimed APIs, host isolation, WAITCNT writes, skipped conditions, stores, and ROM boundaries.
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Refills, IRQ entry, internal-memory execution, HALT/STOP idle, timer advancement, and subsequent IRQ delivery have explicit checks.
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The new resume cases failed on the prior sequential-only path before implementation.
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## Validation result
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Workspace and core/demo tests pass in debug and release on Darwin arm64.
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Formatting, lint checks, rustdoc, preparation tests, native ROM windows, and graphics smoke modes pass.
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Public ARM, Thumb, memory, and BIOS reports match their previous passing results exactly.
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These suites are regression checks, not independent conformance tests for DMA resume timing.
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