79 lines
5.4 KiB
Markdown
79 lines
5.4 KiB
Markdown
# Shared instruction-fetch samples
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## Finding and evidence
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Persistent ARM/Thumb instruction buffering exposed duplicate memory reads in the interpreter.
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The pipeline sampled the new lookahead instruction, then `Memory::begin_cpu_access` reread those bytes for bus history.
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Thumb IWRAM refills also read their target pair once for history and again for instruction buffering.
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With instruction-boundary scheduling, those reads normally saw identical bytes. They still represented the same fetch twice.
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This refactor gives instruction buffering and supported bus-history updates a common captured sample.
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It does not introduce new hardware formulas or change nominal cycle costs.
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Previously reviewed evidence supports this separation:
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- [NanoBoyAdvance at 55b5cf0a](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/arm/arm7tdmi.hh): `Run` fetches the next instruction before execution; refill helpers fetch the target pair.
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- [ares at 6f6786e0](https://github.com/ares-emulator/ares/blob/6f6786e04f0822a3475463df284f313ab8518d51/ares/gba/cpu/memory.cpp): IWRAM updates local addressed lanes; EWRAM halfword reads drive duplicated halves.
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- [Thumb BIOS research](thumb-bios-prefetch.md) and [Thumb open-bus rules](../hardware/cpu.md#thumb-unused-memory-data-reads): BIOS/OAM bus observations use an aligned word, not a universally duplicated halfword.
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These sources were reviewed, not copied into the emulator.
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No physical-hardware measurements or external-emulator differential runs were performed.
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## Sample and consumers
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`memory/fetch.rs` returns an `InstructionFetch` with:
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- Fetch address and instruction state.
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- Strict instruction result or deferred mapped-read error.
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- Supported bus-word observation, when it does not require retained IWRAM lanes.
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ARM samples use the fetched word for both instruction bits and bus observation.
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Thumb samples retain only their selected halfword as instruction bits.
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Supported 16-bit regions duplicate that halfword for bus observation.
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BIOS/OAM samples read the adjacent halfword too, without rereading the instruction bytes.
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Thumb IWRAM supplies the fetched halfword to the existing lane-retaining transaction instead of creating a full bus word.
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For retained pipelines, the CPU passes only its new P+8 or P+4 sample to `begin_cpu_access`.
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The later persistent IWRAM extension also passes newly sampled current/decode entries for cold fills.
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It does not replay the bus observations of retained current/decode instructions.
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The consumer performs no mapped memory read.
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After successful control flow, the same target samples fill the instruction buffer and update local IWRAM history in either state.
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Machine IRQ entry uses this refill path; BIOS vector fetches leave IWRAM lanes unchanged.
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Instruction buffers and BIOS/IWRAM latches remain separate retained state.
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Sampling alone changes no CPU access context, latch, device clock, DMA resume marker, or data-timing trace.
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Instruction errors discard staged history and speculative buffer advances.
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A retry takes a new lookahead sample while retaining the previously committed instruction pair.
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Unavailable lookahead remains diagnostic only when consumed by an instruction or a data read that needs it.
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Strict instruction reads never use protected BIOS or unused-memory data fallback.
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## Current scope and limits
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- Cold fills and cross-state local IWRAM history are now implemented in the [persistent-latch extension](iwram-bus-history.md).
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- Mapped Thumb region crossings now use the actual fetched bus in the [boundary extension](fetch-region-boundaries.md).
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- Unknown IWRAM lanes and unavailable/unsupported fetch observations remain diagnostic.
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- BIOS history commits after successful BIOS instruction execution; target refills do not establish additional BIOS history.
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- All unused-memory data reads within an instruction still use its entry snapshot.
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- DMA remains scheduled between whole instructions. Sampling does not add an interleaving point.
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- Current-instruction and destination-based nominal timing remain unchanged.
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- Per-access device updates, Game Pak prefetch, and exact refill/arbitration timing remain incomplete.
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## Original tests
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CPU tests split the existing internal fetch/execute helpers and mutate lookahead bytes between them.
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ARM, narrow Thumb, wide Thumb, and IWRAM tests then require the originally captured values.
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Those consumption tests failed with the previous duplicate-read path.
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The split is a test-only ownership check, not a hardware DMA experiment.
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Memory tests use explicit expected lane values across mapped regions and both Thumb alignments.
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They also check target-pair consumption after mutation, BIOS snapshot retention, strict errors, short ROMs, and data-context isolation.
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Tests verify that sampling adds no timing or history effects and that failed execution preserves committed history.
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Existing instruction-buffer, bus-history, exception, DMA, and nominal timing tests remain regression coverage.
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## Validation result
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Workspace and core/demo tests pass in debug and release on Darwin arm64.
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Formatting, lint checks, rustdoc, preparation tests, native ROM windows, and graphics smoke modes pass.
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Public ARM, Thumb, memory, and BIOS reports match the previous Thumb-buffer reports exactly, including nominal cycle counts.
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Debug and release reports also match for the same fixture paths.
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These checks validate the refactor against existing behavior, not complete hardware bus or timing conformance.
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