gameboy-rust/docs/references.md

References

External sources consulted while implementing the emulator. Add new sources here, or in a "References" section of the matching docs/hardware/ file when a link explains one specific behavior.

Hardware references used for the core:

• GBATEK ARM instruction cycle times.

• GBATEK GBA system control and WAITCNT, including HALTCNT power-mode selection.

• GBATEK BIOS reset functions, for SoftReset state and restart selection, plus RegisterRamReset flags, RAM bounds, and forced blank.

• GBATEK BIOS halt functions, for wait contracts, STOP clock gating, allowed wake sources, and the clock-off IF note.

• GBATEK BIOS function calling conventions.

• GBATEK BIOS memory-copy services.

• GBATEK BIOS rotation/scaling services, for record layouts, angle units, and output strides.

• VisualBoyAdvance-M BIOS services, reviewed for integer affine rounding, signed matrix intermediates, and SoftReset status handling. Our sine table is generated mathematically.

• GBATEK BIOS arithmetic services.

• GBATEK BIOS decompression services, including BitUnPack descriptor fields, differential-filter headers, Huffman tree layout, and width constraints.

• mGBA BIOS service implementation, reviewed for RegisterRamReset register defaults, angle-polynomial coefficients and quadrant conventions, BitUnPack ordering/offsets, and Huffman tree layout and packing.

• HALTCNT hardware-access tests, for BIOS-only writes and halfword access.

• GBATEK display status and IRQs.

• GBATEK display dimensions and timings.

• mGBA display implementation, used to cross-check hidden-line HBlank IRQs and comparison-write edges.

• GBATEK affine background registers.

• NanoBoyAdvance background implementation, reviewed for internal origins, line-end increments, and affine mosaic behavior.

• GBATEK text and affine map layouts.

• GBATEK background control.

• GBATEK tile/map memory layout.

• mGBA text-background renderer, reviewed for out-of-range fetch behavior.

• GBATEK sprite overview and rendering limits.

• mGBA sprite preprocessing and row preparation, reviewed for inspection costs and aggregate work limits.

• GBATEK sprite attributes.

• GBATEK sprite rotation/scaling parameters.

• GBATEK sprite tile mapping.

• Tonc regular sprites.

• mGBA sprite renderer, reviewed for tile alignment and wrapping.

• GBATEK bitmap backgrounds.

• GBATEK display control.

• GBATEK window registers and priority.

• GBATEK color special effects.

• GBATEK mosaic register.

• NanoBoyAdvance text sampling, reviewed for vertical counter subtraction.

• NanoBoyAdvance mosaic registers, reviewed for phase-preserving size writes and documented timing uncertainties.

• Horizontal sprite mosaic hardware findings, for latch transitions and transparent metadata.

• NanoBoyAdvance sprite pipeline, reviewed for one-row-ahead preparation, mosaic phase, priority updates, and OBJ-window exclusions.

• NanoBoyAdvance display scheduling, reviewed for cycle40 sprite initialization, line227 preparation, and vertical window comparisons on hidden lines.

• NanoBoyAdvance composition, reviewed for palette lookup and horizontal mosaic after sprite preparation.

• mGBA window renderer, reviewed for inverted bounds and vertical edge flags.

• NanoBoyAdvance window implementation, reviewed for persistent vertical flags, four-cycle horizontal comparisons, offscreen columns, and end-edge precedence.

• GBATEK keypad input, for KEYINPUT/KEYCNT fields and selected-button OR/AND matching.

• mGBA keypad sampling and control writes, reviewed for repeated OR requests, AND snapshot suppression, and newly selected held keys.

• NanoBoyAdvance keypad implementation, compared for control access widths; its AND/retrigger behavior differs from the chosen polling model.

• mGBA keypad timing issue, for frontend frame-based input timing limits.

• Tonc hardware interrupts, for keypad source enable and IF/IE bit 12.

• GBATEK memory mirrors, video byte writes, and unused-memory reads, for unused address ranges, ARM PC+8 open bus, byte lanes, the distinct Thumb region/history rules, and PC-dependent BIOS read protection. The Thumb implementation follows its 16-bit-region and BIOS/OAM formulas. IWRAM has persistent local lanes across ARM/Thumb fetches, data accesses, and DMA; mapped boundary snapshots follow the actual fetch region.

• nocash GBA open-bus discussion, for ARM prefetch, repeated Thumb halfwords in 16-bit regions, aligned BIOS/OAM words, and history-dependent IWRAM lanes. Its data-load overwrite note prevents treating P+2 as a universal IWRAM rule.

• mGBA memory implementation, reviewed for GBALoadBad, ARM prefetch sourcing, byte/halfword lane selection, and separate DMA/history behavior. Also reviewed its BIOS region-exit prefetch retention and protected-load lane selection.

• GBATEK GBA memory map and bus widths.

• GBATEK GBA DMA transfers.

• mGBA DMA implementation, used to cross-check masks, repeat behavior, and Game Pak source increments.

• GBATEK GBA timers.

• GBATEK GBA interrupt control.

• GBATEK processor registers and modes.

• GBATEK status transfers.

• GBATEK CPU exceptions.

• GBATEK ARM data processing, including R15/status notes. Its legacy {P} description alone does not establish ARM7 behavior.

• mGBA ARM instruction implementation, reviewed for Rd=15 test/compare SPSR restoration, User/System fallback, and no result write/refill. Also reviewed its word/byte/halfword/signed load ordering: writeback precedes the destination result.

• jsmolka/gba-tests, pinned for independent ARM testing. Reviewed its MIT license, startup, result macros, compare/status tests, and load/writeback alias tests.

• Pinned jsmolka Thumb entry, branch tests, and memory tests, reviewed for r7 failure IDs, success-marker reset, the Thumb-to-ARM evaluation bridge, and empty-list transfer expectations.

• Pinned jsmolka memory entry, mirror tests, and video-byte tests, reviewed for the r12 checkpoint, binary exit targets, limited byte-write assertions, and mode-selection caveats.

• gbadoc memory layout, consulted for VRAM mirror ranges alongside GBATEK's video-memory layout and byte-write rules.

• Pinned jsmolka BIOS test, reviewed for the r12 evaluation checkpoint, internal VBlank wait, and Nintendo-firmware-specific protected-read expectations after boot, SWI, and IRQ.

• armwrestler-gba-fixed and arm7wrestler, considered as test sources; not integrated.

• SingleStepTests ARM7TDMI, considered as an experimental, emulator-generated test source; not integrated.

• GBATEK ARM single data transfers, for address calculation, indexing, load extension, and nominal timing.

• Arm armasm LDR constraints, reviewed to distinguish portable assembly restrictions from the ARM7 alias behavior tested here.

• Pinned halfword alias tests, for loaded-value precedence in pre/post-indexed LDRH aliases.

• GBATEK memory alignment.

• GBATEK multiply instructions.

• GBATEK block transfers.

• GBATEK swaps.

• GBATEK Thumb register operations.

• GBATEK Thumb loads/stores.

• GBATEK Thumb address calculation.

• GBATEK Thumb stack and multiple transfers, for empty-list PC transfers and 64-byte writeback.

• mGBA Thumb transfer implementation and shared memory transfers, reviewed for empty STM/PUSH routing and the extra Thumb instruction width on the stored pipeline PC. This supports executing PC+6, rather than an ordinary PC+4 operand read.

• GBATEK Thumb jumps and calls.

BIOS protected-read root-cause research:

• Smolka Progress Report #6, for firmware-dependent protected reads and the Ruby/Sapphire null-pointer case; the report distinguishes Emerald.
• mGBA: Cracking the GBA BIOS, for BIOS access protection and replacement-versus-external firmware approaches.
• Cult-of-GBA BIOS, reviewed for original boot, SWI, and IRQ exit layout and its MIT license. No source or binary was copied.
• mGBA BIOS implementation, for the explicit post-SWI biosPrefetch compatibility value.
• no$gba BIOS FAQ, for the distinction between simulated firmware services and using a firmware image.

See the root-cause analysis and implementation decision.

Thumb BIOS fetch research:

• NanoBoyAdvance bus at revision 55b5cf0a, for full aligned BIOS latch updates on halfword reads.
• NanoBoyAdvance ARM7TDMI loop at the same revision, for Thumb PC+4 fetch order.
• mGBA CPU loop, compared with its region-exit retention path; not evidence of exact full-word Thumb BIOS readback.
• GBATEK's BIOS/OAM Thumb lane table above supports aligned-word sampling, but describes general unused-memory reads.

See Thumb BIOS prefetch snapshots for the inference, implementation limits, and original regressions.

IWRAM lane-history research:

• mGBA issue 1575, for reported hardware alignment results and IWRAM read/write effects.
• ares IWRAM accesses and bus dispatch, for separate byte-lane retention and debugger isolation.
• jgenesis issue 676 and its correction, for distinguishing the IWRAM latch from reads to other regions.

See persistent IWRAM bus history. The pinned ares helpers also support state-independent local ownership: they do not gate updates on the executing PC or CPU state. The pinned NanoBoyAdvance loop/refill helpers below support driving actual new samples, without replaying retained instruction slots. These were source reviews, not local hardware or external-emulator test runs.

IWRAM refill research:

• ARM7TDMI branch cycle sequence, for destination and destination+instruction-width fetches.
• ARM7TDMI Thumb BL sequence, for the prefix/suffix distinction.
• ARM7TDMI load-multiple sequence, for data-transfer ordering before PC-load refills.
• NanoBoyAdvance refill helpers, reviewed for Thumb target/target+2 fetch order and the following execution fetch.

These sources support bounded refill sampling, not a claim of cycle-accurate pipeline or DMA behavior.

DMA data-latch research:

• NanoBoyAdvance hardware latch test at cc3f4a28, for per-channel ownership, halfword duplication, blocked-source retention, and destination lane selection. Its BSD-3-Clause license was reviewed. No source or ROM was imported.
• NanoBoyAdvance DMA at 55b5cf0a and its data structures, compared with its bus read ordering.
• ares DMA at 6f6786e0, compared with its IWRAM and general-bus dispatch above.

See DMA data-latch findings. Source review is not a local hardware-test pass.

DMA IWRAM continuation research:

• jgenesis bus at fab6e2cc, for DMA read/write dispatch through the same lane-retaining IWRAM helpers as CPU accesses. Its DMA controller and memory storage distinguish channel data from local bus lanes.
• The pinned ares DMA, bus dispatch, and IWRAM helpers above independently use the same local lane ownership.

See the DMA local-lane extension. These source reviews do not establish sub-instruction arbitration, exact CPU resume timing, or hardware conformance.

DMA resume-timing research:

• NanoBoyAdvance force-nseq-access test at cc3f4a28, for equal timer expectations after RAM-source and ROM-source DMA sequences.
• The pinned NanoBoyAdvance bus and ares DMA/bus implementations above explicitly break sequential CPU access after DMA ownership.

See non-sequential CPU resume for the nominal subset and unmodeled refill/prefetch details. The public test was reviewed, not executed. No hardware timing pass is claimed.

ARM/Thumb instruction-buffer research:

• ARM7TDMI instruction pipeline and technical reference manual, for fetch/decode/execute stages and the visible ARM/Thumb PC offsets.
• The pinned NanoBoyAdvance ARM7TDMI Run, ReloadPipeline32, and ReloadPipeline16 helpers above, for retained instructions, pre-execution fetching, and target-pair refill order.
• The ARM branch cycle sequence above, for target and target+instruction-width fetches.
• ARM Thumb branch-with-link timing, for sequential prefix execution and suffix target refill.

See persistent ARM instruction buffering and its Thumb extension. Instruction retention and supported bus snapshots now use shared fetch samples. That refactor reuses the pinned NanoBoyAdvance loop/refill and ares local-lane evidence above. Complete bus history and per-access timing remain incomplete; no new hardware conformance result is claimed.

Fetch-region boundary research:

• The pinned ares getBus and IWRAM helpers above, for address-based dispatch, local lane updates, and the full pre-shift bus value.
• ares OAM reads at 6f6786e0, for full aligned words before CPU halfword selection.
• The pinned jgenesis bus above, for width-dependent general-bus updates and IWRAM's complete local word driving open bus.
• The nocash open-bus discussion above, revisited through a boundary-focused web search. It documents region formulas, not a dedicated boundary hardware test.

See fetch-region boundary findings for source agreement, implementation differences, and retained diagnostics. No physical-hardware or external-emulator differential result is claimed.

Use GBATEK and ARM7TDMI documentation for further hardware work. Only use game ROMs that you may lawfully use. Do not commit game ROMs, BIOS files, or game assets. The ignore file excludes roms/, common game ROM extensions, and save files.