feat(memory): protect CPU BIOS reads with retained ARM prefetch

Retain the supplied image PC+8 snapshot after successful ARM BIOS instructions. CPU data reads from outside BIOS use its byte lanes; reads inside BIOS and host inspection remain mapped reads. Keep nominal timing and diagnostic atomicity. Unknown history, Thumb BIOS execution, and missing lookahead remain explicit limits rather than guessed values.

Add original regressions for ARM/Thumb callers, all CPU modes, widths and rotation, synthetic SWI/IRQ returns, original boot provenance, context isolation, history invalidation, and device progress. No Nintendo firmware or opcode constants are used to synthesize results.

Darwin arm64 validation: 861 workspace tests and 792 core/demo tests in debug and release; 39 Python tests; native ROM windows; all ten demo smoke tests; fmt, clippy, rustdoc, and docs links. Public ARM, Thumb, and memory ROMs still pass. The public BIOS ROM still fails firmware-specific test 1, now reading its actual replacement-BIOS prefetch rather than raw vector bytes.

docs/rom-tests.md

@@ -63,7 +63,8 @@ Rules:
 - `instruction_set` is exactly `arm` or `thumb`. ARM completion addresses must be word-aligned; Thumb addresses must be halfword-aligned.
 - Use the actual Thumb instruction address, without the address bit used by `BX`.
 - Register indices are integers from 0 through 15. Checks read the active register bank.
-- `memory32` addresses must be word-aligned. Reads use the existing little-endian memory bus, including its mapping errors.
+- `memory32` addresses must be word-aligned. Reads use the host inspection path, including mapping errors.
+  BIOS assertions inspect raw mapped bytes, not the protected values seen by CPU code executing outside BIOS.
 - `cpsr` compares the complete current program status register. No mask is applied.
 
 The runner validates the whole manifest before opening or executing any ROM.