feat(memory): protect CPU BIOS reads with retained ARM prefetch
Retain the supplied image PC+8 snapshot after successful ARM BIOS instructions. CPU data reads from outside BIOS use its byte lanes; reads inside BIOS and host inspection remain mapped reads. Keep nominal timing and diagnostic atomicity. Unknown history, Thumb BIOS execution, and missing lookahead remain explicit limits rather than guessed values. Add original regressions for ARM/Thumb callers, all CPU modes, widths and rotation, synthetic SWI/IRQ returns, original boot provenance, context isolation, history invalidation, and device progress. No Nintendo firmware or opcode constants are used to synthesize results. Darwin arm64 validation: 861 workspace tests and 792 core/demo tests in debug and release; 39 Python tests; native ROM windows; all ten demo smoke tests; fmt, clippy, rustdoc, and docs links. Public ARM, Thumb, and memory ROMs still pass. The public BIOS ROM still fails firmware-specific test 1, now reading its actual replacement-BIOS prefetch rather than raw vector bytes.
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@ -98,7 +98,8 @@ Host inspection, ROM-suite memory assertions, instruction fetches, and DMA do no
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Limits remain explicit:
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- Thumb open bus depends on instruction region, alignment, and prior bus data; it remains unsupported.
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- BIOS-protected reads, unused/write-only I/O reads, DMA latches, and disabled-RAM reads are not modeled here.
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- [BIOS-protected reads](bios.md#cpu-bios-read-protection) use separate retained ARM BIOS snapshots.
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- Unused/write-only I/O reads, DMA latches, and disabled-RAM reads are not modeled here.
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- Missing BIOS, truncated ROM, unsupported I/O, and save-memory accesses retain their existing diagnostics.
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- Unused-memory writes remain diagnostics rather than ignored hardware writes. Swaps cannot silently discard their write.
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- No persistent pipeline or bus history exists. Self-modifying code and DMA-to-CPU bus transitions are not hardware-accurate.
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