feat(memory): protect CPU BIOS reads with retained ARM prefetch
Retain the supplied image PC+8 snapshot after successful ARM BIOS instructions. CPU data reads from outside BIOS use its byte lanes; reads inside BIOS and host inspection remain mapped reads. Keep nominal timing and diagnostic atomicity. Unknown history, Thumb BIOS execution, and missing lookahead remain explicit limits rather than guessed values. Add original regressions for ARM/Thumb callers, all CPU modes, widths and rotation, synthetic SWI/IRQ returns, original boot provenance, context isolation, history invalidation, and device progress. No Nintendo firmware or opcode constants are used to synthesize results. Darwin arm64 validation: 861 workspace tests and 792 core/demo tests in debug and release; 39 Python tests; native ROM windows; all ten demo smoke tests; fmt, clippy, rustdoc, and docs links. Public ARM, Thumb, and memory ROMs still pass. The public BIOS ROM still fails firmware-specific test 1, now reading its actual replacement-BIOS prefetch rather than raw vector bytes.
This commit is contained in:
0xrsydn
parent
6e736c634b
commit
c31a703db4
11 changed files with 399 additions and 16 deletions
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@ -13,6 +13,8 @@ pub use exception::Exception;
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pub use status::Mode;
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mod transfer;
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#[cfg(test)]
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mod bios_access_tests;
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#[cfg(test)]
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mod compare_psr_tests;
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#[cfg(test)]
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@ -206,7 +208,7 @@ impl Cpu {
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// Always clear the access context, including on diagnostic errors.
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memory.begin_cpu_access(self.pc(), self.instruction_set);
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let result = self.execute_instruction(instruction, memory);
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memory.end_cpu_access();
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memory.end_cpu_access(result.is_ok());
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result
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}
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309
crates/gba-core/src/cpu/bios_access_tests.rs
Normal file
309
crates/gba-core/src/cpu/bios_access_tests.rs
Normal file
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@ -0,0 +1,309 @@
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//! Original synthetic BIOS images; no Nintendo firmware or expected firmware constants.
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use super::*;
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use crate::{
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io::TIMER_BASE,
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machine::{Machine, StepKind},
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memory::{BIOS_SIZE, ROM_START},
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timing::StepTiming,
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};
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const ENTRY: u32 = 0x100;
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const DATA: u32 = 0xf233_80a5;
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const OTHER: u32 = 0x1234_5678;
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const LDR: u32 = 0xe590_1000; // LDR r1, [r0]
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const BX_R4: u32 = 0xe12f_ff14;
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fn word(bytes: &mut [u8], address: u32, value: u32) {
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bytes[address as usize..address as usize + 4].copy_from_slice(&value.to_le_bytes());
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}
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fn image() -> Vec<u8> {
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let mut bios = vec![0x55; BIOS_SIZE];
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word(&mut bios, ENTRY, BX_R4);
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word(&mut bios, ENTRY + 8, DATA);
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word(&mut bios, 0x200, BX_R4);
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word(&mut bios, 0x208, OTHER);
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bios
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}
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fn bus(instruction: u32, bios: Vec<u8>) -> Memory {
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let rom = [instruction, LDR, OTHER, OTHER];
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Memory::with_bios(rom.into_iter().flat_map(u32::to_le_bytes).collect(), bios).unwrap()
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}
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fn leave_bios(memory: &mut Memory, thumb: bool) -> Cpu {
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let mut cpu = Cpu::new(ENTRY);
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cpu.registers[4] = ROM_START | u32::from(thumb);
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cpu.step(memory).unwrap();
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assert_eq!(cpu.pc(), ROM_START);
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cpu
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}
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#[test]
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fn protected_bios_loads_use_latched_lanes_for_arm_and_thumb_callers() {
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for (arm, thumb, values) in [
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(
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LDR,
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0x6801,
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[0xf233_80a5, 0xa5f2_3380, 0x80a5_f233, 0x3380_a5f2],
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),
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(0xe5d0_1000, 0x7801, [0xa5, 0x80, 0x33, 0xf2]),
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(
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0xe1d0_10b0,
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0x8801,
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[0x80a5, 0xa500_0080, 0xf233, 0x3300_00f2],
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),
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(
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0xe1d0_10d0,
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0x5681,
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[0xffff_ffa5, 0xffff_ff80, 0x33, 0xffff_fff2],
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),
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(
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0xe1d0_10f0,
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0x5e81,
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[0xffff_80a5, 0xffff_ff80, 0xffff_f233, 0xffff_fff2],
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),
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] {
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for is_thumb in [false, true] {
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for address in [0, ENTRY, 0x3ffc] {
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for (low, value) in values.into_iter().enumerate() {
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let mut memory = bus(if is_thumb { thumb } else { arm }, image());
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let mut cpu = leave_bios(&mut memory, is_thumb);
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cpu.registers[0] = address + low as u32;
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cpu.flags.carry = true;
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let mut expected = cpu.clone();
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expected.registers[1] = value;
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expected.registers[15] += if is_thumb { 2 } else { 4 };
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let timing = cpu.step_timed(&mut memory).unwrap();
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assert_eq!(
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cpu, expected,
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"arm={arm:#010x} thumb={is_thumb} address={address:#x} lane={low}"
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);
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assert_eq!(timing.data_cycles, 1);
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assert_eq!(timing.internal_cycles, 1);
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assert_eq!(memory.cycles(), 0);
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}
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}
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}
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}
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}
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#[test]
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fn protection_depends_on_executing_address_not_processor_mode() {
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for mode in [
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Mode::User,
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Mode::System,
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Mode::Fiq,
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Mode::Irq,
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Mode::Supervisor,
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Mode::Abort,
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Mode::Undefined,
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] {
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for thumb in [false, true] {
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let mut bios = image();
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word(&mut bios, 0x200, if thumb { 0x6801 } else { LDR });
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word(&mut bios, 0x300, OTHER);
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let mut memory = bus(if thumb { 0x6801 } else { LDR }, bios);
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let mut cpu = leave_bios(&mut memory, thumb);
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cpu.apply_status(0xb000_00c0 | (u32::from(thumb) << 5) | mode as u32, mode);
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cpu.registers[0] = 0x300;
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cpu.step(&mut memory).unwrap(); // Outside BIOS: even privileged modes cannot read raw bytes.
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assert_eq!(cpu.registers[1], DATA);
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cpu.registers[15] = 0x200;
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cpu.step(&mut memory).unwrap(); // Inside BIOS: both instruction sets can read raw data.
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assert_eq!(cpu.registers[1], OTHER);
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assert_eq!(
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cpu.cpsr(),
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0xb000_00c0 | (u32::from(thumb) << 5) | mode as u32
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);
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}
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}
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}
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#[test]
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fn host_inspection_does_not_change_the_latch_or_expose_cpu_protected_bytes() {
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let mut memory = bus(LDR, image());
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let mut cpu = leave_bios(&mut memory, false);
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for address in [0, 0x200, 0x3ffc] {
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assert_eq!(
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memory.read32(address).unwrap(),
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if address == 0x200 { BX_R4 } else { 0x5555_5555 }
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);
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}
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assert_eq!(memory.read32(ENTRY + 8).unwrap(), DATA);
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assert_eq!(memory.read32(0x208).unwrap(), OTHER);
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assert_eq!(memory.write32(0, 0), Err(MemoryError::ReadOnly(0)));
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], DATA);
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cpu.step(&mut memory).unwrap(); // More ROM execution must not replace the BIOS latch.
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assert_eq!(cpu.registers[1], DATA);
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}
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#[test]
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fn bios_reentry_and_exception_returns_refresh_the_image_derived_value() {
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let mut memory = bus(LDR, image());
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let mut cpu = leave_bios(&mut memory, false);
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cpu.registers[15] = 0x200;
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cpu.step(&mut memory).unwrap();
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], OTHER);
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for swi in [false, true] {
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let mut bios = image();
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let vector = if swi { 8 } else { 0x18 };
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word(
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&mut bios,
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vector,
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if swi { 0xe1b0_f00e } else { 0xe25e_f004 },
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); // MOVS/SUBS pc,lr
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word(&mut bios, vector + 8, OTHER);
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let mut memory = bus(if swi { 0xef00_0000 } else { LDR }, bios);
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let mut cpu = leave_bios(&mut memory, false);
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if swi {
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cpu.step(&mut memory).unwrap();
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} else {
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cpu.enter_exception(Exception::Irq);
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}
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assert_eq!(cpu.pc(), vector);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.mode(), Mode::System);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], OTHER);
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}
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}
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#[test]
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fn unknown_bios_history_returns_a_diagnostic_not_raw_bytes_or_a_magic_value() {
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for bios in [false, true] {
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let mut memory = if bios {
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bus(LDR, image())
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} else {
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Memory::new(LDR.to_le_bytes().to_vec()).unwrap()
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};
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if bios {
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assert_eq!(memory.read32(0).unwrap(), 0x5555_5555);
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}
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let mut cpu = Cpu::new(ROM_START);
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut memory),
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Err(CpuError::Memory(MemoryError::Unmapped(0)))
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);
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assert_eq!(cpu, before);
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}
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}
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#[test]
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fn diagnostic_steps_keep_previous_bios_history_but_skipped_instructions_refresh_it() {
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for instruction in [0xe7f0_00f0, LDR] {
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let mut bios = image();
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word(&mut bios, 0x200, instruction);
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let mut memory = bus(LDR, bios);
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let mut cpu = leave_bios(&mut memory, false);
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cpu.registers[15] = 0x200;
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cpu.registers[0] = 0x0e00_0000;
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let before = cpu.clone();
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assert!(cpu.step_timed(&mut memory).is_err());
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assert_eq!(cpu, before);
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cpu.registers[15] = ROM_START;
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cpu.registers[0] = 0;
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], DATA);
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}
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let mut bios = image();
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word(&mut bios, 0x200, 0x0590_1000); // LDREQ skipped with Z clear.
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let mut memory = bus(LDR, bios);
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let mut cpu = leave_bios(&mut memory, false);
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cpu.registers[15] = 0x200;
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cpu.step(&mut memory).unwrap();
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cpu.registers[15] = ROM_START;
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], OTHER);
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}
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#[test]
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fn thumb_bios_execution_and_missing_lookahead_invalidate_unsupported_history() {
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for (pc, thumb) in [(0x200, true), (0x3ff8, false), (0x3ffc, false)] {
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let mut bios = image();
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word(&mut bios, pc, if thumb { 0x4720 } else { BX_R4 }); // Thumb BX r4 or ARM BX r4
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let mut memory = bus(LDR, bios);
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let mut cpu = leave_bios(&mut memory, false);
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cpu.registers[15] = pc;
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cpu.instruction_set = if thumb {
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InstructionSet::Thumb
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} else {
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InstructionSet::Arm
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};
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.pc(), ROM_START);
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut memory),
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Err(CpuError::Memory(MemoryError::Unmapped(0)))
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);
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assert_eq!(cpu, before);
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}
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}
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#[test]
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fn bios_block_loads_share_the_latch_but_unused_memory_uses_rom_prefetch() {
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let mut memory = bus(0xe8b0_000e, image()); // LDMIA r0!, {r1-r3}
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let mut cpu = leave_bios(&mut memory, false);
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cpu.step(&mut memory).unwrap();
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assert_eq!(&cpu.registers[1..4], &[DATA; 3]);
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assert_eq!(cpu.registers[0], 12);
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let mut memory = bus(LDR, image());
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let mut cpu = leave_bios(&mut memory, false);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], DATA);
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cpu.registers[0] = 0x4000;
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], OTHER);
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}
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#[test]
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fn original_boot_protected_read_matches_its_actual_last_bios_snapshot() {
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let rom = [0xe3a0_0000, LDR]; // MOV r0,#0; LDR r1,[r0]
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let mut machine =
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crate::bios::boot(rom.into_iter().flat_map(u32::to_le_bytes).collect()).unwrap();
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let bios = crate::bios::image();
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let mut last_bios_pc = None;
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for _ in 0..128 {
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if machine.cpu().pc() == ROM_START {
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break;
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}
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let pc = machine.cpu().pc();
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assert!(pc < BIOS_SIZE as u32);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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last_bios_pc = Some(pc);
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}
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assert_eq!(machine.cpu().pc(), ROM_START);
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let offset = last_bios_pc.unwrap() as usize + 8;
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let expected = u32::from_le_bytes(bios[offset..offset + 4].try_into().unwrap());
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assert_ne!(expected, machine.memory().read32(0).unwrap());
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machine.step().unwrap();
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[1], expected);
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}
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#[test]
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fn protected_reads_charge_one_data_access_before_device_progress() {
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let mut memory = bus(LDR, image());
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let cpu = leave_bios(&mut memory, false);
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memory.write32(TIMER_BASE, 0x0080_0000).unwrap();
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let mut machine = Machine::new(cpu, memory);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[1], DATA);
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assert_eq!(
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machine.last_timing(),
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StepTiming {
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code_cycles: 8,
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data_cycles: 1,
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internal_cycles: 1,
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idle_cycles: 0
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}
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);
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assert_eq!(machine.cycles(), 10);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 10);
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}
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@ -61,7 +61,8 @@ struct CpuAccess {
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/// Work/video/palette RAM, OAM, cartridge ROM, optional BIOS, and supported I/O.
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/// ARM data reads from unused memory return a PC+8 snapshot when available.
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/// BIOS protection, Thumb open bus, and DMA bus latches are not modeled.
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/// CPU data reads of BIOS from outside BIOS use its retained ARM PC+8 snapshot.
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/// Thumb BIOS prefetch, general Thumb open bus, and DMA bus latches are not modeled.
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pub struct Memory {
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external_ram: Vec<u8>,
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internal_ram: Vec<u8>,
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@ -74,6 +75,7 @@ pub struct Memory {
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cycles: u64,
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data_timing: Cell<Option<DataTiming>>,
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cpu_access: Option<CpuAccess>,
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bios_prefetch: Option<u32>,
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scanline_capture: Option<video::capture::Capture>,
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sprite_pipeline: pipeline::SpritePipeline,
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}
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@ -95,6 +97,7 @@ impl Memory {
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cycles: 0,
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data_timing: Cell::new(None),
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cpu_access: None,
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bios_prefetch: None,
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scanline_capture: None,
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sprite_pipeline: pipeline::SpritePipeline::default(),
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})
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@ -346,8 +349,14 @@ impl Memory {
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Some(u32::from_le_bytes(bytes))
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}
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pub(crate) fn end_cpu_access(&mut self) {
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self.cpu_access = None;
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pub(crate) fn end_cpu_access(&mut self, succeeded: bool) {
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if let Some(access) = self.cpu_access.take() {
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if succeeded && access.pc < BIOS_SIZE as u32 {
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// Commit only successful instruction snapshots under our diagnostic policy.
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// Thumb BIOS execution or missing lookahead invalidates the known value.
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self.bios_prefetch = access.arm_prefetch;
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}
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}
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}
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fn can_write_power_control(&self) -> bool {
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@ -415,6 +424,18 @@ impl Memory {
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// Multi-byte reads use this helper to avoid charging each byte as a bus access.
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fn read_byte(&self, address: u32) -> Result<u8, MemoryError> {
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if address < BIOS_SIZE as u32
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&& self.bios.is_some()
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&& self
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.cpu_access
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.is_some_and(|access| access.pc >= BIOS_SIZE as u32)
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{
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// Protect CPU data reads, not host inspection or BIOS instruction fetches.
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return self
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.bios_prefetch
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.map(|word| (word >> ((address & 3) * 8)) as u8)
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.ok_or(MemoryError::Unmapped(address));
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}
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if matches!(address, 0x0000_4000..=0x01ff_ffff | 0x1000_0000..=0xffff_ffff) {
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if let Some(word) = self.cpu_access.and_then(|access| access.arm_prefetch) {
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return Ok((word >> ((address & 3) * 8)) as u8);
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|
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