383 lines
14 KiB
Rust
383 lines
14 KiB
Rust
//! GBA I/O subset: DMA, timers, interrupts, WAITCNT, display, and polled input.
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//! Timer phase resets on enable or clock-source changes. Hardware startup delays,
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//! shared prescaler phase, audio events, and interrupt delivery delays are not modeled.
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use crate::{
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display::{Display, DisplayPosition, CYCLES_PER_LINE, HBLANK_START, VISIBLE_LINES},
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dma::{Dma, DmaError, Transfer, DMA_BASE, DMA_END},
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input::Buttons,
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};
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pub const DISPCNT: u32 = 0x0400_0000;
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pub const GREENSWAP: u32 = 0x0400_0002;
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pub const DISPSTAT: u32 = 0x0400_0004;
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pub const VCOUNT: u32 = 0x0400_0006;
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pub const BG0CNT: u32 = 0x0400_0008;
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pub const BG1CNT: u32 = 0x0400_000a;
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pub const BG2CNT: u32 = 0x0400_000c;
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pub const BG3CNT: u32 = 0x0400_000e;
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pub const BG0HOFS: u32 = 0x0400_0010;
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pub const BG0VOFS: u32 = 0x0400_0012;
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pub const BG1HOFS: u32 = 0x0400_0014;
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pub const BG1VOFS: u32 = 0x0400_0016;
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pub const BG2HOFS: u32 = 0x0400_0018;
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pub const BG2VOFS: u32 = 0x0400_001a;
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pub const BG3HOFS: u32 = 0x0400_001c;
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pub const BG3VOFS: u32 = 0x0400_001e;
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pub const BG2PA: u32 = 0x0400_0020;
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pub const BG2PB: u32 = 0x0400_0022;
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pub const BG2PC: u32 = 0x0400_0024;
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pub const BG2PD: u32 = 0x0400_0026;
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pub const BG2X: u32 = 0x0400_0028;
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pub const BG2Y: u32 = 0x0400_002c;
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pub const BG3PA: u32 = 0x0400_0030;
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pub const BG3PB: u32 = 0x0400_0032;
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pub const BG3PC: u32 = 0x0400_0034;
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pub const BG3PD: u32 = 0x0400_0036;
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pub const BG3X: u32 = 0x0400_0038;
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pub const BG3Y: u32 = 0x0400_003c;
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pub const WIN0H: u32 = 0x0400_0040;
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pub const WIN1H: u32 = 0x0400_0042;
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pub const WIN0V: u32 = 0x0400_0044;
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pub const WIN1V: u32 = 0x0400_0046;
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pub const WININ: u32 = 0x0400_0048;
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pub const WINOUT: u32 = 0x0400_004a;
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pub const MOSAIC: u32 = 0x0400_004c;
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pub const BLDCNT: u32 = 0x0400_0050;
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pub const BLDALPHA: u32 = 0x0400_0052;
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pub const BLDY: u32 = 0x0400_0054;
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pub const KEYINPUT: u32 = 0x0400_0130;
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pub const TIMER_BASE: u32 = 0x0400_0100;
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pub const IE: u32 = 0x0400_0200;
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pub const IF: u32 = 0x0400_0202;
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pub const WAITCNT: u32 = 0x0400_0204;
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pub const IME: u32 = 0x0400_0208;
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pub const POSTFLG: u32 = 0x0400_0300;
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pub const HALTCNT: u32 = 0x0400_0301;
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const IRQ_MASK: u16 = 0x3fff;
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#[derive(Debug, Default, Clone, PartialEq, Eq)]
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struct Timer {
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reload: u16,
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counter: u16,
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control: u8,
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phase: u32,
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}
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impl Timer {
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fn enabled(&self) -> bool {
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self.control & 0x80 != 0
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}
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fn count_up(&self) -> bool {
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self.control & 4 != 0
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}
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fn set_control(&mut self, value: u8, index: usize) {
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let value = value & if index == 0 { 0xc3 } else { 0xc7 };
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let start = !self.enabled() && value & 0x80 != 0;
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if start {
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self.counter = self.reload;
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}
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if start || (self.control ^ value) & 7 != 0 {
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self.phase = 0;
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}
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self.control = value;
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}
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/// Next independently clocked overflow. Cascaded timers receive their
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/// pulses at a predecessor's event and cannot overflow earlier.
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fn next_overflow(&self) -> Option<u32> {
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if !self.enabled() || self.count_up() {
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return None;
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}
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let divisor = [1, 64, 256, 1024][usize::from(self.control & 3)];
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Some((0x1_0000 - u32::from(self.counter)) * divisor - self.phase)
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}
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/// Advance without looping once per cycle or overflow. Return the number of
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/// overflows, not just a boolean, so cascaded timers receive every pulse.
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fn advance(&mut self, cycles: u32, previous_overflows: u64) -> u64 {
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if !self.enabled() {
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return 0;
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}
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let ticks = if self.count_up() {
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previous_overflows
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} else {
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let divisor = [1, 64, 256, 1024][usize::from(self.control & 3)];
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let elapsed = u64::from(self.phase) + u64::from(cycles);
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self.phase = (elapsed % divisor) as u32;
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elapsed / divisor
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};
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let until_overflow = 0x1_0000 - u64::from(self.counter);
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if ticks < until_overflow {
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self.counter += ticks as u16;
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return 0;
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}
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let remaining = ticks - until_overflow;
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let period = 0x1_0000 - u64::from(self.reload);
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self.counter = (u64::from(self.reload) + remaining % period) as u16;
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1 + remaining / period
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}
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}
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#[derive(Debug, Default, Clone, PartialEq, Eq)]
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pub(crate) struct Io {
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timers: [Timer; 4],
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enable: u16,
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pending: u16,
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master_enable: bool,
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waitcnt: u16,
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dispcnt: u16,
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greenswap: bool,
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mosaic: u16,
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vertical_mosaic: crate::video::mosaic::VerticalMosaic,
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backgrounds: [crate::video::Background; 4],
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effects: crate::video::effects::Effects,
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window_edges: crate::video::windows::WindowEdges,
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horizontal_windows: crate::video::windows::horizontal::HorizontalWindows,
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buttons: Buttons,
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display: Display,
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dma: Dma,
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postflg: bool,
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halted: bool,
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}
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impl Io {
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pub(crate) fn mapped(address: u32) -> bool {
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matches!(address, 0x0400_0000..=0x0400_0057 | DMA_BASE..=DMA_END | 0x0400_0100..=0x0400_010f | 0x0400_0130..=0x0400_0131 | 0x0400_0200..=0x0400_020b | POSTFLG..=0x0400_0303)
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}
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pub(crate) fn read8(&self, address: u32) -> Option<u8> {
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if (DMA_BASE..=DMA_END).contains(&address) {
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return Some(self.dma.read8(address));
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}
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let value = match address & !1 {
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DISPCNT => self.dispcnt,
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GREENSWAP => u16::from(self.greenswap),
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DISPSTAT => self.display.status(),
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VCOUNT => self.display.position().scanline,
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BG0CNT..=BG3CNT => self.backgrounds[((address - BG0CNT) / 2) as usize].control,
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BG0HOFS..=0x0400_003e => 0, // Scroll/affine registers are write-only; not open bus.
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WIN0H..=WIN1V | MOSAIC | 0x0400_004e | BLDY | 0x0400_0056 => 0, // Write-only/unused; no open bus yet.
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WININ => self.effects.inside,
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WINOUT => self.effects.outside,
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BLDCNT => self.effects.control,
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BLDALPHA => self.effects.alpha,
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KEYINPUT => self.buttons.keyinput(),
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0x0400_0100..=0x0400_010e => {
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let timer = &self.timers[((address - TIMER_BASE) / 4) as usize];
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if address & 2 == 0 {
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timer.counter
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} else {
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u16::from(timer.control)
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}
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}
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IE => self.enable,
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IF => self.pending,
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WAITCNT => self.waitcnt,
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0x0400_0206 => 0,
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IME => u16::from(self.master_enable),
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0x0400_020a => 0,
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POSTFLG => u16::from(self.postflg), // HALTCNT reads zero, not an open-bus model.
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0x0400_0302 => 0,
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_ => return None,
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};
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Some(value.to_le_bytes()[(address & 1) as usize])
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}
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/// The memory bus validates every byte before calling this method.
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pub(crate) fn write8(&mut self, address: u32, value: u8) {
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debug_assert!(Self::mapped(address));
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if (DMA_BASE..=DMA_END).contains(&address) {
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self.dma.write8(address, value);
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return;
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}
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match address & !1 {
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DISPCNT => self.dispcnt = replace_byte(self.dispcnt, address, value) & 0xfff7,
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GREENSWAP if address & 1 == 0 => self.greenswap = value & 1 != 0,
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DISPSTAT => self.pending |= self.display.write_status(address & 1 != 0, value),
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VCOUNT | KEYINPUT => {} // Read-only; writes are ignored.
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BG0CNT..=BG3CNT => {
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let index = ((address - BG0CNT) / 2) as usize;
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let control = &mut self.backgrounds[index].control;
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// Overflow applies to affine BG2/BG3 only; bits 4 and 5 are unused.
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*control = replace_byte(*control, address, value)
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& if index < 2 { 0xdfcf } else { 0xffcf };
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}
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BG0HOFS..=BG3VOFS => {
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let bg = &mut self.backgrounds[((address - BG0HOFS) / 4) as usize];
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let offset = if address & 2 == 0 {
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&mut bg.x
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} else {
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&mut bg.y
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};
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*offset = replace_byte(*offset, address, value) & 0x1ff;
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}
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BG2PA..=0x0400_003e => {
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let index = 2 + ((address - BG2PA) / 16) as usize;
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let position = self.display.position();
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let after_row = u32::from(position.line_cycle) >= HBLANK_START
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|| u32::from(position.scanline) >= VISIBLE_LINES;
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self.backgrounds[index]
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.affine
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.write8((address & 15) as usize, value, after_row);
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}
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WIN0H..=WIN1V => {
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let index = ((address - WIN0H) / 2) as usize;
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let bounds = if index < 2 {
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&mut self.effects.horizontal[index]
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} else {
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&mut self.effects.vertical[index - 2]
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};
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*bounds = replace_byte(*bounds, address, value);
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}
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MOSAIC => self.mosaic = replace_byte(self.mosaic, address, value),
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WININ | WINOUT | BLDCNT | BLDALPHA | BLDY => {
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let (latch, mask) = match address & !1 {
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WININ => (&mut self.effects.inside, 0x3f3f),
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WINOUT => (&mut self.effects.outside, 0x3f3f),
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BLDCNT => (&mut self.effects.control, 0x3fff),
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BLDALPHA => (&mut self.effects.alpha, 0x1f1f),
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_ => (&mut self.effects.brightness, 0x1f),
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};
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*latch = replace_byte(*latch, address, value) & mask;
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}
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0x0400_0100..=0x0400_010e => {
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let index = ((address - TIMER_BASE) / 4) as usize;
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let timer = &mut self.timers[index];
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if address & 2 == 0 {
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// Merge into the reload latch, never the visible counter.
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timer.reload = replace_byte(timer.reload, address, value);
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} else if address & 1 == 0 {
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timer.set_control(value, index);
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}
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}
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IE => self.enable = replace_byte(self.enable, address, value) & IRQ_MASK,
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WAITCNT => self.waitcnt = replace_byte(self.waitcnt, address, value) & 0x5fff,
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IF => self.pending &= !(u16::from(value) << ((address & 1) * 8)),
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IME if address & 1 == 0 => self.master_enable = value & 1 != 0,
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POSTFLG if address == POSTFLG => self.postflg = value & 1 != 0,
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POSTFLG => {
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// The bus has already rejected STOP and enforced CPU write access.
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debug_assert_eq!(value & 0x80, 0);
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self.halted = true;
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}
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_ => {} // Unused I/O bytes ignore writes.
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}
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self.wake_if_requested();
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}
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pub(crate) fn halted(&self) -> bool {
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self.halted
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}
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fn wake_if_requested(&mut self) {
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// Wake-up ignores IME and CPSR.I. It does not acknowledge IF.
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if self.enable & self.pending != 0 {
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self.halted = false;
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}
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}
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/// Bound an idle batch by the next display edge or independent timer overflow.
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/// Display edges keep this finite even without an enabled wake source.
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pub(crate) fn next_event_cycles(&self) -> u32 {
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self.timers
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.iter()
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.filter_map(Timer::next_overflow)
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.fold(self.display.next_event_cycles(), u32::min)
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}
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pub(crate) fn display_position(&self) -> DisplayPosition {
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self.display.position()
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}
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pub(crate) fn set_buttons(&mut self, buttons: Buttons) {
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self.buttons = buttons;
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}
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pub(crate) fn display_control(&self) -> u16 {
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self.dispcnt
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}
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pub(crate) fn video_settings(&self, captured: bool) -> crate::video::RenderSettings<'_> {
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crate::video::RenderSettings {
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control: self.dispcnt,
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prepared_objects: None,
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internal_affine: captured,
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vertical_windows: captured.then_some(self.window_edges.active),
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horizontal_windows: captured.then_some(&self.horizontal_windows),
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green_swap: self.greenswap,
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mosaic: self.mosaic,
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vertical_mosaic: captured.then_some(self.vertical_mosaic),
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backgrounds: &self.backgrounds,
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effects: &self.effects,
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}
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}
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pub(crate) fn waitcnt(&self) -> u16 {
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self.waitcnt
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}
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pub(crate) fn irq_pending(&self) -> bool {
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self.master_enable && self.enable & self.pending != 0
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}
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pub(crate) fn next_dma(&self) -> Result<Option<Transfer>, DmaError> {
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self.dma.next()
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}
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pub(crate) fn complete_dma_unit(&mut self, channel: usize) {
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self.pending |= self.dma.complete_unit(channel);
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self.wake_if_requested();
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}
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pub(crate) fn advance(&mut self, cycles: u32) {
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// Hardware state tracks time even when host-side frame capture is disabled.
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let position = self.display.position();
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let phase = u32::from(position.scanline) * CYCLES_PER_LINE + u32::from(position.line_cycle);
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self.window_edges
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.advance(phase, cycles, self.effects.vertical);
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self.horizontal_windows
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.advance(phase, cycles, self.effects.horizontal);
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let mode = self.dispcnt & 7;
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for index in 2..4 {
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let active = self.dispcnt & (0x100 << index) != 0
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&& if index == 2 {
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(1..=5).contains(&mode)
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} else {
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mode == 2
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};
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let (height, counter) = if self.backgrounds[index].control & 0x40 != 0 {
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(
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u32::from((self.mosaic >> 4) & 15) + 1,
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self.vertical_mosaic.background,
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)
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} else {
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(1, 0)
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};
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self.backgrounds[index]
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.affine
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.advance(phase, cycles, active, height, counter);
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}
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self.vertical_mosaic.advance(phase, cycles, self.mosaic);
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let (vblank, hblank) = self.display.dma_events(cycles);
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self.dma.trigger(vblank, hblank);
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self.pending |= self.display.advance(cycles);
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let mut overflows = 0;
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for (index, timer) in self.timers.iter_mut().enumerate() {
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overflows = timer.advance(cycles, overflows);
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if overflows != 0 && timer.control & 0x40 != 0 {
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// Pending flags latch even if IE, IME, or CPSR.I blocks delivery.
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self.pending |= 1 << (3 + index);
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}
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}
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self.wake_if_requested();
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}
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}
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fn replace_byte(previous: u16, address: u32, value: u8) -> u16 {
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let shift = (address & 1) * 8;
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(previous & !(0xff << shift)) | (u16::from(value) << shift)
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}
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