223 lines
8.5 KiB
Rust
223 lines
8.5 KiB
Rust
//! Nominal ARM7 instruction-cycle summaries, separate from instruction semantics.
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//! Code costs use source-fetch and target-pair addresses; data costs use actual bus accesses.
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//! Source access kinds remain instruction-local nominal summaries.
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use super::{Cpu, CpuError, InstructionSet};
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use crate::{
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memory::Memory,
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timing::{bus_cycles, refill_cycles, AccessKind, AccessWidth, StepTiming},
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};
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#[derive(Default)]
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struct Summary {
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code_kind: AccessKind,
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refill: bool,
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internal: u32,
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}
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impl Summary {
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fn branch() -> Self {
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Self {
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refill: true,
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..Self::default()
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}
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}
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fn transfer(load: bool, pc: bool) -> Self {
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Self {
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code_kind: if load {
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AccessKind::Sequential
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} else {
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AccessKind::NonSequential
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},
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refill: load && pc,
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internal: u32::from(load),
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}
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}
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}
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impl InstructionSet {
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fn access_width(self) -> AccessWidth {
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match self {
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Self::Arm => AccessWidth::Word,
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Self::Thumb => AccessWidth::Halfword,
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}
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}
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}
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impl Cpu {
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/// Execute one instruction and return its nominal cycle cost. Like Cpu::step,
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/// this does not advance device time or sample interrupts. Machine does that.
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/// Failed instructions discard their timing trace and retain existing diagnostics.
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pub fn step_timed(&mut self, memory: &mut Memory) -> Result<StepTiming, CpuError> {
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let fetched = self.fetch(memory)?;
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let instruction = fetched.instruction;
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let summary = match self.instruction_set {
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InstructionSet::Arm => self.arm_summary(instruction),
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InstructionSet::Thumb => self.thumb_summary(instruction),
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};
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let fetch_address = fetched.lookahead.address();
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let width = self.instruction_set.access_width();
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// A WAITCNT store affects subsequent instructions, not this code access.
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let waitcnt = memory.waitcnt();
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let code_kind = memory.cpu_code_kind(summary.code_kind);
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memory.begin_data_timing();
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let result = self.execute_fetched(fetched, memory);
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let data_cycles = memory.end_data_timing();
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result?;
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let mut code_cycles = bus_cycles(waitcnt, fetch_address, width, code_kind);
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if summary.refill {
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code_cycles += refill_cycles(waitcnt, self.pc(), self.instruction_set.access_width());
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}
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Ok(StepTiming {
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code_cycles,
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data_cycles,
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internal_cycles: summary.internal,
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idle_cycles: 0,
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})
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}
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/// Accept IRQ between instructions, discard the old-state fetch, then refill ARM.
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/// A missing discarded fetch cannot prevent entry or become a current-slot error.
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pub(crate) fn take_irq_timed(&mut self, memory: &mut Memory) -> Option<StepTiming> {
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let state = self.instruction_set;
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let address = self.pc().wrapping_add(2 * state.width());
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if !self.take_interrupt(memory.irq_pending(), false) {
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return None;
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}
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let waitcnt = memory.waitcnt();
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let kind = memory.cpu_code_kind(AccessKind::Sequential);
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let fetch = memory.fetch_instruction(address, state);
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memory.discarded_cpu_fetch(&fetch);
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self.refill_pipeline(memory);
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Some(StepTiming {
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code_cycles: bus_cycles(waitcnt, fetch.address(), state.access_width(), kind)
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+ refill_cycles(waitcnt, self.pc(), self.instruction_set.access_width()),
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..StepTiming::default()
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})
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}
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fn arm_summary(&self, instruction: u32) -> Summary {
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if !self.flags.condition_passed(instruction >> 28) {
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return Summary::default();
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}
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if instruction & 0x0f00_0000 == 0x0f00_0000
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|| instruction & 0x0fff_fff0 == 0x012f_ff10
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|| instruction & 0x0e00_0000 == 0x0a00_0000
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{
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return Summary::branch();
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}
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if instruction & 0x0fbf_0fff == 0x010f_0000
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|| instruction & 0x0fb0_fff0 == 0x0120_f000
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|| instruction & 0x0fb0_f000 == 0x0320_f000
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{
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return Summary::default(); // MRS/MSR overlap the data-processing space.
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}
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if instruction & 0x0e00_0000 == 0x0800_0000 {
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let list = instruction & 0xffff;
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return Summary::transfer(
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instruction & (1 << 20) != 0,
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list == 0 || list & 0x8000 != 0,
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);
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}
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if instruction & 0x0fb0_0ff0 == 0x0100_0090 {
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return Summary {
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internal: 1,
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..Summary::default()
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}; // SWP: two N data accesses
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}
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if instruction & 0x0f80_00f0 == 0x0080_0090 {
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let signed = instruction & (1 << 22) != 0;
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let multiplier = self.registers[((instruction >> 8) & 15) as usize];
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return Summary {
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internal: multiply_cycles(multiplier, signed)
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+ 1
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+ u32::from(instruction & (1 << 21) != 0),
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..Summary::default()
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};
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}
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if instruction & 0x0fc0_00f0 == 0x0000_0090 {
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let multiplier = self.registers[((instruction >> 8) & 15) as usize];
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return Summary {
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internal: multiply_cycles(multiplier, true)
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+ u32::from(instruction & (1 << 21) != 0),
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..Summary::default()
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};
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}
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if instruction & 0x0e00_0090 == 0x0000_0090 {
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return Summary::transfer(instruction & (1 << 20) != 0, false);
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}
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if instruction & 0x0c00_0000 == 0x0400_0000 {
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return Summary::transfer(instruction & (1 << 20) != 0, (instruction >> 12) & 15 == 15);
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}
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let test = (8..=11).contains(&((instruction >> 21) & 15));
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Summary {
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refill: !test && (instruction >> 12) & 15 == 15,
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internal: u32::from(instruction & (1 << 25) == 0 && instruction & (1 << 4) != 0),
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..Summary::default()
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}
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}
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// Share the existing control-flow classification with bounded bus history.
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// A PC write can refill even when its target equals the sequential address.
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pub(super) fn instruction_refills(&self, instruction: u32) -> bool {
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match self.instruction_set {
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InstructionSet::Arm => self.arm_summary(instruction).refill,
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InstructionSet::Thumb => self.thumb_summary(instruction).refill,
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}
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}
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fn thumb_summary(&self, instruction: u32) -> Summary {
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match instruction {
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0x4000..=0x43ff => {
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let opcode = (instruction >> 6) & 15;
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let internal = match opcode {
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2 | 3 | 4 | 7 => 1,
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// Thumb MUL maps the incoming destination to ARM's Rs.
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13 => multiply_cycles(self.registers[(instruction & 7) as usize], true),
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_ => 0,
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};
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Summary {
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internal,
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..Summary::default()
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}
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}
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0x4400..=0x47ff => {
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let opcode = (instruction >> 8) & 3;
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let destination = (instruction & 7) | ((instruction >> 4) & 8);
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if opcode == 3 || (opcode != 1 && destination == 15) {
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Summary::branch()
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} else {
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Summary::default()
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}
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}
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0x4800..=0x4fff => Summary::transfer(true, false),
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0x5000..=0x5fff => Summary::transfer((instruction >> 9) & 7 >= 3, false),
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0x6000..=0x9fff => Summary::transfer(instruction & (1 << 11) != 0, false),
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0xb400..=0xb5ff | 0xbc00..=0xbdff => Summary::transfer(
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instruction & (1 << 11) != 0,
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instruction & 0x100 != 0 || instruction & 0xff == 0,
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),
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0xc000..=0xcfff => {
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Summary::transfer(instruction & (1 << 11) != 0, instruction & 255 == 0)
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}
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0xd000..=0xddff if self.flags.condition_passed((instruction >> 8) & 15) => {
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Summary::branch()
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}
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0xdf00..=0xdfff | 0xe000..=0xe7ff | 0xf800..=0xffff => Summary::branch(),
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// Thumb BL prefix fetches once; its suffix adds the target N+S pair.
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_ => Summary::default(),
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}
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}
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}
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fn multiply_cycles(value: u32, signed: bool) -> u32 {
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for bytes in 1..=3 {
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let mask = u32::MAX << (bytes * 8);
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let high = value & mask;
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if high == 0 || signed && high == mask {
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return bytes;
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}
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}
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4
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}
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