20176716d9
Stores to I/O addresses with no register returned Unmapped and stopped the machine. Hardware ignores them. Emulated writes there now pay their bus cost and change nothing; host writes stay strict. The unmodeled internal memory control register at 0x04xx0800 and all unused I/O reads remain diagnostics. Rollback tests that used unused I/O as their failing word now run the block on to a register that rejects the stored value: SIOMULTI2 outside multiplayer mode, an RCNT GPIO serial IRQ, or 64-sample wave playback. Where no reachable register can fail (JOYSTAT, POSTFLG/HALTCNT, IME, DMA3CNT), the test now checks that the block commits and the unused word is ignored. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01HhfHfHEuzv2AUTd6erW1gU
466 lines
17 KiB
Rust
466 lines
17 KiB
Rust
use gba_core::{
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cpu::{Cpu, Mode},
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display::{CYCLES_PER_FRAME, CYCLES_PER_LINE, HBLANK_START, LINES_PER_FRAME, VBLANK_START},
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io::{DISPCNT, DISPSTAT, IE, IF, IME, TIMER_BASE, VCOUNT},
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machine::{FrameRunError, Machine, StepKind},
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memory::{Memory, MemoryError, BIOS_SIZE, ROM_START},
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};
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fn memory() -> Memory {
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Memory::new(vec![]).unwrap()
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}
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#[test]
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fn display_starts_at_line_zero_with_comparison_match_but_no_irq() {
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let bus = memory();
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assert_eq!(bus.read16(DISPSTAT).unwrap(), 4);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 0);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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assert_eq!(bus.display_position().scanline, 0);
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assert_eq!(bus.display_position().line_cycle, 0);
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assert_eq!(bus.display_position().frames, 0);
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assert_eq!(bus.display_position().vblanks, 0);
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assert_eq!(bus.cycles(), 0);
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}
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#[test]
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fn hblank_status_starts_at_1006_not_at_the_last_visible_pixel() {
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let mut bus = memory();
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bus.advance_cycles(960);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 2, 0);
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bus.advance_cycles(45);
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assert_eq!(bus.display_position().line_cycle, 1005);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 2, 0);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 2, 2);
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bus.advance_cycles(225);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 0);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 2, 2);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 1);
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assert_eq!(bus.display_position().line_cycle, 0);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 7, 0);
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}
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#[test]
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fn vblank_starts_at_160_clears_at_227_and_line_count_wraps_at_228() {
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let mut bus = memory();
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bus.advance_cycles(VBLANK_START - 1);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 159);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 3, 2);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 160);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 3, 1);
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assert_eq!(bus.display_position().vblanks, 1);
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bus.advance_cycles(67 * CYCLES_PER_LINE - 1);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 226);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 3, 3);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 227);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 3, 0);
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assert_eq!(bus.display_position().frames, 0);
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bus.advance_cycles(CYCLES_PER_LINE);
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assert_eq!(bus.read32(DISPSTAT).unwrap(), 4); // Compare zero matches again
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assert_eq!(bus.display_position().frames, 1);
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assert_eq!(bus.display_position().vblanks, 1);
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assert_eq!(bus.cycles(), 280_896);
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}
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#[test]
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fn hblank_irq_occurs_on_every_line_including_hidden_lines() {
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let mut bus = memory();
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bus.write16(DISPSTAT, 0x10).unwrap();
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for line in 0..LINES_PER_FRAME {
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bus.advance_cycles(HBLANK_START - 1);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(VCOUNT).unwrap(), line as u16);
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assert_eq!(bus.read16(IF).unwrap(), 2);
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bus.write16(IF, 2).unwrap();
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bus.advance_cycles(CYCLES_PER_LINE - HBLANK_START);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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}
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assert_eq!(bus.display_position().frames, 1);
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}
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#[test]
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fn vblank_and_compare_requests_latch_without_ie_or_ime_and_acknowledge_independently() {
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let mut bus = memory();
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bus.write16(DISPSTAT, 0xa028).unwrap(); // VBlank + VCount=160
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bus.advance_cycles(VBLANK_START);
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assert_eq!(bus.read16(IF).unwrap(), 5);
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assert!(!bus.irq_pending());
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bus.write16(IE, 5).unwrap();
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assert!(!bus.irq_pending());
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bus.write32(IME, 1).unwrap();
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assert!(bus.irq_pending());
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bus.write16(IF, 1).unwrap();
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assert_eq!(bus.read16(IF).unwrap(), 4);
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assert!(bus.irq_pending());
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bus.write16(IF, 4).unwrap();
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assert!(!bus.irq_pending());
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bus.advance_cycles(0);
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bus.advance_cycles(10);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.advance_cycles(CYCLES_PER_FRAME - 10);
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assert_eq!(bus.read16(IF).unwrap(), 5);
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}
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#[test]
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fn register_masks_read_only_fields_and_word_accesses_are_coherent() {
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let mut bus = memory();
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bus.advance_cycles(17 * CYCLES_PER_LINE + HBLANK_START);
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bus.write32(DISPSTAT, u32::MAX).unwrap();
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assert_eq!(bus.read16(DISPSTAT).unwrap(), 0xff3a);
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assert_eq!(bus.read16(VCOUNT).unwrap(), 17);
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assert_eq!(bus.read32(DISPSTAT).unwrap(), 0x0011_ff3a);
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bus.write8(VCOUNT, 200).unwrap();
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bus.write8(VCOUNT + 1, 0xff).unwrap();
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assert_eq!(bus.read16(VCOUNT).unwrap(), 17);
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bus.write8(DISPSTAT, 0).unwrap();
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assert_eq!(bus.read16(DISPSTAT).unwrap(), 0xff02);
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bus.write8(DISPSTAT + 1, 17).unwrap();
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assert_eq!(bus.read16(DISPSTAT).unwrap(), 0x1106);
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assert_eq!(bus.read8(DISPSTAT).unwrap(), 6);
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assert_eq!(bus.read8(DISPSTAT + 1).unwrap(), 17);
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assert_eq!(bus.read8(VCOUNT + 1).unwrap(), 0);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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assert_eq!(
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bus.write16(DISPSTAT + 1, 0),
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Err(MemoryError::Unaligned(DISPSTAT + 1))
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);
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assert_eq!(bus.read16(DISPSTAT).unwrap(), 0x1106);
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}
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#[test]
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fn writing_comparator_can_create_one_immediate_rising_match_request() {
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let mut bus = memory();
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bus.advance_cycles(7 * CYCLES_PER_LINE);
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bus.write16(DISPSTAT, 0x0620).unwrap();
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 4, 0);
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bus.write8(DISPSTAT + 1, 7).unwrap();
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 4, 4);
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assert_eq!(bus.read16(IF).unwrap(), 4);
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bus.write16(IF, 4).unwrap();
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bus.write8(DISPSTAT + 1, 7).unwrap(); // Already matches
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bus.write8(DISPSTAT, 0).unwrap();
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bus.write8(DISPSTAT, 0x20).unwrap(); // Enabling alone does not create a match edge
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bus.advance_cycles(1);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.write8(DISPSTAT + 1, 6).unwrap();
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bus.write8(DISPSTAT + 1, 7).unwrap();
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assert_eq!(bus.read16(IF).unwrap(), 4);
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}
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#[test]
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fn zero_comparator_irq_waits_for_the_next_line_zero_entry() {
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let mut bus = memory();
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bus.write16(DISPSTAT, 0x20).unwrap();
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.advance_cycles(CYCLES_PER_FRAME - 1);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(IF).unwrap(), 4);
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bus.write16(IF, 4).unwrap();
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bus.advance_cycles(1);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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}
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#[test]
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fn out_of_range_comparator_values_never_match() {
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let mut bus = memory();
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for compare in 228..=255 {
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bus.write16(DISPSTAT, (compare << 8) | 0x20).unwrap();
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bus.advance_cycles(CYCLES_PER_FRAME);
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assert_eq!(bus.read16(DISPSTAT).unwrap() & 4, 0);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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}
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}
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#[test]
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fn enabling_vblank_or_hblank_irq_does_not_replay_an_active_status() {
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let mut bus = memory();
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bus.advance_cycles(VBLANK_START);
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bus.write16(DISPSTAT, 8).unwrap();
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bus.advance_cycles(0);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.advance_cycles(CYCLES_PER_FRAME - 1);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(IF).unwrap(), 1);
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let mut bus = memory();
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bus.advance_cycles(HBLANK_START);
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bus.write16(DISPSTAT, 0x10).unwrap();
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bus.advance_cycles(CYCLES_PER_LINE - 1);
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assert_eq!(bus.read16(IF).unwrap(), 0);
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bus.advance_cycles(1);
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assert_eq!(bus.read16(IF).unwrap(), 2);
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}
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#[test]
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fn forced_blank_and_display_mode_changes_do_not_stop_or_reset_the_clock() {
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let mut bus = memory();
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bus.write16(DISPCNT, 0x80).unwrap();
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bus.write16(DISPSTAT, 0x18).unwrap();
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bus.advance_cycles(VBLANK_START);
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let position = bus.display_position();
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assert_eq!(bus.read16(IF).unwrap(), 3);
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bus.write16(DISPCNT, 0x403).unwrap();
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assert_eq!(bus.display_position(), position);
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bus.advance_cycles(CYCLES_PER_FRAME);
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assert_eq!(bus.display_position().vblanks, 2);
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assert_eq!(bus.display_position().scanline, 160);
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}
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#[test]
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fn timer_and_display_events_can_latch_in_the_same_clock_batch() {
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let mut bus = memory();
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let reload = 65536 - HBLANK_START;
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bus.write32(TIMER_BASE, 0x00c0_0000 | reload).unwrap();
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bus.write16(DISPSTAT, 0x10).unwrap();
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bus.advance_cycles(HBLANK_START);
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assert_eq!(bus.read16(IF).unwrap(), 0x0a);
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bus.write16(IF, 2).unwrap();
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assert_eq!(bus.read16(IF).unwrap(), 8);
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}
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#[test]
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fn bulk_clock_advances_match_a_cycle_by_cycle_reference() {
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for compare in [0_u16, 1, 160, 226, 227, 255] {
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let mut bus = memory();
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bus.write16(DISPSTAT, (compare << 8) | 0x38).unwrap();
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let mut line = 0_u16;
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let mut cycle = 0_u16;
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let mut frames = 0_u64;
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let mut vblanks = 0_u64;
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for chunk in [
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0,
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1,
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959,
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46,
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226,
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17_777,
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CYCLES_PER_FRAME * 2 + 99,
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1232,
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77,
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] {
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let mut pending = 0;
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for _ in 0..chunk {
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cycle += 1;
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if cycle == 1006 {
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pending |= 2;
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}
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if cycle == 1232 {
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cycle = 0;
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line += 1;
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if line == 228 {
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line = 0;
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frames += 1;
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}
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if line == 160 {
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vblanks += 1;
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pending |= 1;
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}
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if line == compare {
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pending |= 4;
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}
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}
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}
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bus.advance_cycles(chunk);
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assert_eq!(
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bus.read16(IF).unwrap(),
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pending,
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"compare {compare}, chunk {chunk}"
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);
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let flags = u16::from((160..227).contains(&line))
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| (u16::from(cycle >= 1006) << 1)
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| (u16::from(line == compare) << 2);
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assert_eq!(bus.read16(DISPSTAT).unwrap(), (compare << 8) | 0x38 | flags);
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let position = bus.display_position();
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assert_eq!(
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(
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position.scanline,
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position.line_cycle,
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position.frames,
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position.vblanks
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),
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(line, cycle, frames, vblanks)
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);
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bus.write16(IF, 7).unwrap();
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}
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}
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}
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#[test]
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fn maximum_batches_preserve_multi_frame_counts_and_do_not_overflow_u32() {
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let mut bus = memory();
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bus.write16(DISPSTAT, 0xa038).unwrap();
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for multiplier in 1..=2_u64 {
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bus.advance_cycles(u32::MAX);
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let total = multiplier * u64::from(u32::MAX);
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let phase = total % u64::from(CYCLES_PER_FRAME);
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let position = bus.display_position();
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assert_eq!(position.frames, total / u64::from(CYCLES_PER_FRAME));
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assert_eq!(
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position.vblanks,
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(total + u64::from(CYCLES_PER_FRAME - VBLANK_START)) / u64::from(CYCLES_PER_FRAME)
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);
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assert_eq!(
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u64::from(position.scanline),
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phase / u64::from(CYCLES_PER_LINE)
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);
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assert_eq!(
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u64::from(position.line_cycle),
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phase % u64::from(CYCLES_PER_LINE)
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);
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assert_eq!(bus.read16(IF).unwrap(), 7);
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assert_eq!(bus.cycles(), total);
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bus.write16(IF, 7).unwrap();
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}
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}
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#[test]
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fn display_sources_enter_an_original_irq_handler_acknowledge_and_return() {
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for (control, source, edge) in [
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(8, 1, VBLANK_START),
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(0x10, 2, HBLANK_START),
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(0xa020, 4, VBLANK_START),
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] {
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let mut bios = vec![0; BIOS_SIZE];
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for (index, instruction) in [0xe1c1_20b2_u32, 0xe280_0001, 0xe25e_f004]
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.into_iter()
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.enumerate()
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{
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// STRH r2,[r1,#2] (IF); ADD r0,r0,#1; SUBS pc,lr,#4
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let offset = 0x18 + index * 4;
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bios[offset..offset + 4].copy_from_slice(&instruction.to_le_bytes());
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}
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let rom = [
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0xe3a0_1301_u32,
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0xe281_1c02,
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0xe3a0_2000 | source,
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0xe283_3001,
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0xeaff_fffe,
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]
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.into_iter()
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.flat_map(u32::to_le_bytes)
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.collect();
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let mut bus = Memory::with_bios(rom, bios).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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for _ in 0..3 {
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cpu.step(&mut bus).unwrap();
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}
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bus.write16(DISPSTAT, control).unwrap();
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bus.write16(IE, source as u16).unwrap();
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bus.write32(IME, 1).unwrap();
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bus.advance_cycles(edge - 1);
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let mut machine = Machine::new(cpu, bus);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[3], 1);
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assert_eq!(machine.memory().read16(IF).unwrap(), source as u16);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.cpu().mode(), Mode::Irq);
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assert_eq!(machine.cpu().pc(), 0x18);
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assert_eq!(machine.cpu().registers()[14], ROM_START + 20);
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for _ in 0..3 {
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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}
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assert_eq!(machine.cpu().registers()[0], 1);
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assert_eq!(machine.cpu().mode(), Mode::System);
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assert_eq!(machine.cpu().pc(), ROM_START + 16);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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}
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}
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#[test]
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fn failed_block_store_does_not_change_window_controls_or_advance_display() {
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// STMIA r12!,{r0-r11} stores WININ/WINOUT through SOUND3CNT_X. Unused words are
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// ignored. With 64-sample wave mode selected, r11 requests playback, a diagnostic.
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let operands = [
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(12, 0x0400_0048),
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(0, 0x3f),
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(1, 1),
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(10, 0xa0),
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(11, 0x8000),
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];
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let offset = (operands.len() as u32 - 1) * 4;
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let mut code: Vec<u32> = operands
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.iter()
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.map(|&(register, _)| 0xe59f_0000 | (register as u32) << 12 | offset)
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.collect();
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code.push(0xe8ac_0fff);
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code.extend(operands.iter().map(|&(_, value)| value));
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let mut bus = Memory::new(code.into_iter().flat_map(u32::to_le_bytes).collect()).unwrap();
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bus.write16(0x0400_0084, 0x80).unwrap(); // Master sound enable.
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bus.write16(0x0400_0070, 0xa0).unwrap(); // Wave: 64-sample mode, DAC on.
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let mut cpu = Cpu::new(ROM_START);
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for _ in operands {
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cpu.step(&mut bus).unwrap();
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}
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bus.advance_cycles(7 * CYCLES_PER_LINE);
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let before = cpu.clone();
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let position = bus.display_position();
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let mut machine = Machine::new(cpu, bus);
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let error = machine.step().unwrap_err();
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assert!(
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error.to_string().contains("64-sample wave playback"),
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"{error}"
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);
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.memory().display_position(), position);
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assert_eq!(machine.memory().read32(gba_core::io::WININ).unwrap(), 0);
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assert_eq!(machine.memory().read16(DISPSTAT).unwrap(), 0);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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}
|
|
|
|
#[test]
|
|
fn frame_runner_waits_for_next_vblank_event_not_an_already_set_flag() {
|
|
let mut bus = memory();
|
|
bus.write32(0x0300_0000, 0xeaff_fffe).unwrap(); // 3-cycle IWRAM self-branch
|
|
bus.advance_cycles(VBLANK_START - 2);
|
|
let mut machine = Machine::new(Cpu::new(0x0300_0000), bus);
|
|
assert_eq!(machine.run_until_vblank(1).unwrap(), 1);
|
|
assert_eq!(machine.memory().display_position().line_cycle, 1);
|
|
assert_eq!(machine.memory().display_position().vblanks, 1);
|
|
let steps = machine
|
|
.run_until_vblank((CYCLES_PER_FRAME / 3) as usize)
|
|
.unwrap();
|
|
assert_eq!(steps, (CYCLES_PER_FRAME / 3) as usize);
|
|
assert_eq!(machine.memory().display_position().line_cycle, 1);
|
|
assert_eq!(machine.memory().display_position().vblanks, 2);
|
|
}
|
|
|
|
#[test]
|
|
fn frame_runner_limits_and_cpu_errors_preserve_completed_progress_only() {
|
|
let mut bus = memory();
|
|
bus.write32(0x0300_0000, 0xeaff_fffe).unwrap();
|
|
let mut machine = Machine::new(Cpu::new(0x0300_0000), bus);
|
|
assert_eq!(
|
|
machine.run_until_vblank(0),
|
|
Err(FrameRunError::StepLimit(0))
|
|
);
|
|
assert_eq!(machine.cycles(), 0);
|
|
assert_eq!(
|
|
machine.run_until_vblank(2),
|
|
Err(FrameRunError::StepLimit(2))
|
|
);
|
|
assert_eq!(machine.cycles(), 6);
|
|
assert_eq!(machine.memory().display_position().line_cycle, 6);
|
|
machine
|
|
.memory_mut()
|
|
.write32(0x0300_0000, 0xf000_0000)
|
|
.unwrap();
|
|
let position = machine.memory().display_position();
|
|
assert!(matches!(
|
|
machine.run_until_vblank(10),
|
|
Err(FrameRunError::Cpu(_))
|
|
));
|
|
// The already buffered branch executes once and refills from the patched word.
|
|
// The unsupported instruction then fails without further device progress.
|
|
assert_eq!(
|
|
machine.memory().display_position().line_cycle,
|
|
position.line_cycle + 3
|
|
);
|
|
assert_eq!(machine.cycles(), 9);
|
|
}
|