207 lines
8.2 KiB
Rust
207 lines
8.2 KiB
Rust
//! Original disconnected external-clock probes. No partner, clock edges, or completion is invented.
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use gba_core::{
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cpu::Cpu,
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dma::DMA_BASE,
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io::{HALTCNT, IE, IF, IME, RCNT, SIOCNT, SIODATA32, SIODATA8},
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machine::{Machine, StepKind},
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memory::{Memory, ROM_START},
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};
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fn memory() -> Memory {
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Memory::new(0xeaff_fffe_u32.to_le_bytes().to_vec()).unwrap()
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}
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#[test]
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fn every_low_control_byte_retains_normal_control_bits_without_immediate_completion() {
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let mut bus = memory();
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for high in [0, 0x10, 0x40, 0x50] {
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for previous in [0x0003, 0x1000, 0x4080, 0x5082] {
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for low in 0..=u8::MAX {
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bus.write16(SIOCNT, previous).unwrap();
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bus.write8(SIOCNT, low).unwrap();
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assert_eq!(
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bus.read16(SIOCNT).unwrap(),
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(previous & 0x5000) | u16::from(low & 0x8b) | 4
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);
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bus.write8(SIOCNT + 1, high).unwrap();
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assert_eq!(
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bus.read16(SIOCNT).unwrap(),
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(u16::from(high) << 8) | u16::from(low & 0x8b) | 4
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);
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assert_eq!(bus.read16(IF).unwrap() & 0x80, 0);
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}
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}
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}
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}
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#[test]
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fn disconnected_external_requests_wait_at_both_widths_and_rates_until_software_cancels() {
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let mut bus = memory();
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bus.write16(IE, 0x80).unwrap();
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bus.write16(IME, 1).unwrap();
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for control in [0x4080, 0x4082, 0x5080, 0x5082] {
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bus.write32(SIODATA32, 0x12345678).unwrap();
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bus.write16(SIODATA8, 0xab).unwrap();
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bus.write16(SIOCNT, control).unwrap();
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for cycles in [1, 63, 64, 512, 2048, 1000000, u32::MAX] {
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bus.advance_cycles(cycles);
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assert_eq!(bus.read16(SIOCNT).unwrap(), control | 4);
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assert_eq!(bus.read32(SIODATA32).unwrap(), 0x12345678);
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assert_eq!(bus.read16(SIODATA8).unwrap(), 0xab);
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assert_eq!(bus.read16(IF).unwrap() & 0x80, 0);
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assert!(!bus.irq_pending());
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}
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// Rewriting start does not manufacture a clock edge or transfer completion.
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bus.write16(SIOCNT, control).unwrap();
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bus.write8(SIOCNT, 8).unwrap(); // Explicit software cancellation; SO high.
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assert_eq!(bus.read16(SIOCNT).unwrap(), (control & 0x5000) | 12);
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assert_eq!(bus.read32(SIODATA32).unwrap(), 0x12345678);
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assert_eq!(bus.read16(SIODATA8).unwrap(), 0xab);
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}
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}
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#[test]
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fn gpio_selection_does_not_turn_a_retained_start_bit_into_a_transfer_or_irq() {
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let mut bus = memory();
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bus.write16(RCNT, 0x8040).unwrap(); // SI output low, GPIO IRQ disabled.
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bus.write16(SIOCNT, 0x5080).unwrap();
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bus.advance_cycles(1000000);
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assert_eq!(bus.read16(SIOCNT).unwrap(), 0x5080);
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bus.write16(RCNT, 0).unwrap(); // Disconnected normal SI is pulled high.
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bus.advance_cycles(1000000);
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assert_eq!(bus.read16(SIOCNT).unwrap(), 0x5084);
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assert_eq!(bus.read16(IF).unwrap() & 0x80, 0);
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// Selecting internal clock starts the pending request, but not instant completion.
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bus.write8(SIOCNT, 0x81).unwrap();
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assert_eq!(bus.read16(SIOCNT).unwrap(), 0x5085);
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bus.write16(SIOCNT, 0x5001).unwrap(); // Cancel first, then select internal clock while idle.
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assert_eq!(bus.read16(SIOCNT).unwrap(), 0x5005);
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}
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#[test]
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fn external_request_does_not_wake_halt_or_stop() {
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for stop in [false, true] {
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let mut bus = memory();
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bus.write16(IE, 0x80).unwrap();
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bus.write16(IME, 1).unwrap();
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bus.write16(SIOCNT, 0x5080).unwrap();
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bus.write8(HALTCNT, if stop { 0x80 } else { 0 }).unwrap();
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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for _ in 0..100 {
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assert_eq!(
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machine.step().unwrap(),
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if stop {
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StepKind::StopIdle
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} else {
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StepKind::HaltIdle
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}
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);
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}
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assert_eq!(machine.stopped(), stop);
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assert_eq!(machine.halted(), !stop);
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assert_eq!(machine.memory().read16(IF).unwrap() & 0x80, 0);
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x5084);
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assert_eq!(machine.cycles() == 0, stop);
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}
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}
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fn prepared(thumb: bool, instruction: u32, value: u32) -> Machine {
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let code = if thumb {
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vec![
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0xe59f0010, 0xe59f1010, 0xe28f2001, 0xe12fff12, 0xe7fe8001, 0xeafffffe, SIOCNT, value,
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]
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} else {
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vec![
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0xe59f0008,
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0xe59f1008,
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instruction,
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0xeafffffe,
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SIOCNT,
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value,
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]
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};
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let mut bus = Memory::new(code.into_iter().flat_map(u32::to_le_bytes).collect()).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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for _ in 0..if thumb { 4 } else { 2 } {
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cpu.step(&mut bus).unwrap();
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}
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bus.write16(SIOCNT, 0x1003).unwrap();
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Machine::new(cpu, bus)
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}
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#[test]
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fn arm_and_thumb_external_starts_complete_as_instructions_not_as_serial_transfers() {
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for thumb in [false, true] {
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for value in [0x5084, 0x7080] {
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let mut machine = prepared(thumb, 0xe1c010b0, value); // STRH r1,[r0]
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let cpu = machine.cpu().clone();
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if value == 0x5084 {
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x5084);
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assert!(machine.cycles() > 0);
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for _ in 0..100 {
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machine.step().unwrap();
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}
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x5084);
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assert_eq!(machine.memory().read16(IF).unwrap() & 0x80, 0);
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} else {
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let error = machine.step().unwrap_err();
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assert!(error.to_string().contains("multiplayer/UART serial mode"));
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assert_eq!(machine.cpu(), &cpu);
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assert_eq!(machine.cycles(), 0);
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x1007);
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assert_eq!(machine.step(), Err(error));
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}
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}
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}
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}
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#[test]
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fn invalid_word_and_block_writes_do_not_leave_a_partial_external_start() {
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let mut bus = memory();
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bus.write16(SIOCNT, 0x5000).unwrap();
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bus.write16(SIODATA8, 0x12).unwrap();
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assert!(bus.write32(SIOCNT, 0x00ab2080).is_err());
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assert_eq!(bus.read16(SIOCNT).unwrap(), 0x5004);
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assert_eq!(bus.read16(SIODATA8).unwrap(), 0x12);
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bus.write32(SIOCNT, 0x00ab5080).unwrap();
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assert_eq!(bus.read16(SIOCNT).unwrap(), 0x5084);
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assert_eq!(bus.read16(SIODATA8).unwrap(), 0xab);
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let mut machine = prepared(false, 0xe8a00006, 0x00ab5080); // STMIA r0!,{r1,r2}; second word unmapped.
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let before = machine.cpu().clone();
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let error = machine.step().unwrap_err();
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assert!(error.to_string().contains("unmapped memory at 0x0400012c"));
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), 0);
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x1007);
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assert_eq!(machine.memory().read16(SIODATA8).unwrap(), 0);
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assert_eq!(machine.step(), Err(error));
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}
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#[test]
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fn dma_start_preserves_serial_wait_and_reports_only_dma_completion() {
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let mut bus = memory();
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bus.write32(0x02000000, 0x00ab7080).unwrap();
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bus.write32(DMA_BASE, 0x02000000).unwrap();
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bus.write32(DMA_BASE + 4, SIOCNT).unwrap();
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bus.write32(DMA_BASE + 8, 0xc4000001).unwrap();
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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let error = machine.step().unwrap_err();
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assert!(error.to_string().contains("multiplayer/UART serial mode"));
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assert_eq!(machine.step(), Err(error));
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assert_eq!(machine.cycles(), 0);
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 4);
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assert_eq!(machine.memory().read16(SIODATA8).unwrap(), 0);
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machine
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.memory_mut()
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.write32(0x02000000, 0x00ab5080)
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.unwrap();
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 0 });
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x5084);
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assert_eq!(machine.memory().read16(SIODATA8).unwrap(), 0xab);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0x100); // DMA IRQ, not serial IRQ.
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machine.memory_mut().advance_cycles(1000000);
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assert_eq!(machine.memory().read16(SIOCNT).unwrap(), 0x5084);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0x100);
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}
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