273 lines
11 KiB
Rust
273 lines
11 KiB
Rust
use gba_core::{
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cpu::{Cpu, CpuError, InstructionSet, Mode},
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io::{IE, IF, IME, TIMER_BASE, WAITCNT},
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machine::{Machine, MachineError, StepKind},
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memory::{Memory, MemoryError, BIOS_SIZE, ROM_START},
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};
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use gba_demos::timer_demo::{timer_demo, TIMER_DEMO_STEPS};
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fn words(values: &[u32]) -> Vec<u8> {
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values
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.iter()
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.flat_map(|value| value.to_le_bytes())
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.collect()
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}
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fn timer(bus: &mut Memory) {
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bus.write32(TIMER_BASE, 0x00c0_ffff).unwrap();
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bus.write16(IE, 8).unwrap();
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bus.write32(IME, 1).unwrap();
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}
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fn pending_timer(bus: &mut Memory) {
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timer(bus);
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bus.advance_cycles(1);
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bus.write16(TIMER_BASE + 2, 0).unwrap();
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}
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// Load test operands through real instructions, without exposing CPU setters.
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fn prepared(instruction: u32, operands: &[(usize, u32)]) -> Machine {
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let offset = (operands.len() as u32 - 1) * 4;
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let mut code: Vec<u32> = operands
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.iter()
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.map(|&(register, _)| 0xe59f_0000 | (register as u32) << 12 | offset)
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.collect();
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code.push(instruction);
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code.extend(operands.iter().map(|&(_, value)| value));
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let mut bus = Memory::new(words(&code)).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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for _ in operands {
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cpu.step(&mut bus).unwrap();
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}
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Machine::new(cpu, bus)
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}
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#[test]
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fn timer_demo_configures_hardware_in_cpu_code_and_handles_exactly_one_irq() {
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let mut machine = timer_demo().unwrap();
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let mut entries = 0;
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for step in 1..=TIMER_DEMO_STEPS {
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let kind = machine.step().unwrap();
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assert!(machine.last_timing().total() > 0);
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if kind == StepKind::IrqEntry {
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entries += 1;
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assert_eq!(step, 13); // Nominal timing model, not a hardware measurement
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assert_eq!(machine.cpu().pc(), 0x18);
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assert_eq!(machine.cpu().spsr(), Some(0x1f));
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assert_eq!(machine.cpu().registers()[14], ROM_START + 0x30);
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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}
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}
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assert_eq!(entries, 1);
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assert_eq!(machine.cycles(), 151); // Initial non-refill ROM fetch is S+S, not N+S.
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assert_eq!(machine.cpu().mode(), Mode::System);
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assert_eq!(machine.cpu().pc(), ROM_START + 0x2c);
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assert_eq!(machine.cpu().registers()[10], 1);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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assert_eq!(machine.memory().read16(TIMER_BASE + 2).unwrap(), 0);
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// Start no longer pays its preceding nine cycles; stop now pays its two bus cycles.
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xfff4);
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for _ in 0..100 {
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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}
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assert_eq!(machine.cpu().registers()[10], 1);
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}
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#[test]
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fn overflow_after_instruction_is_sampled_on_next_step() {
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let mut bus = Memory::new(words(&[0xe280_0001, 0xe280_0001])).unwrap();
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timer(&mut bus);
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[0], 1);
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assert_eq!(machine.cpu().pc(), ROM_START + 4);
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.cpu().registers()[0], 1); // Interrupted instruction did not execute
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assert_eq!(machine.cpu().registers()[14], ROM_START + 8);
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assert_eq!(machine.cycles(), 14); // Instruction fetch 6; IRQ source fetch 6 + BIOS pair 2.
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}
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#[test]
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fn missing_vector_errors_only_after_completed_irq_entry() {
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let mut bus = Memory::new(vec![]).unwrap();
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pending_timer(&mut bus);
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry); // Missing discarded ROM fetch cannot prevent IRQ entry
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let before = machine.cpu().clone();
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let cycles = machine.cycles();
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assert_eq!(
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machine.step(),
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Err(MachineError::Cpu(CpuError::Memory(MemoryError::Unmapped(
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0x18
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))))
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);
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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}
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#[test]
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fn cpu_mask_defers_irq_until_msr_unmasks_it() {
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let mut bios = vec![0; BIOS_SIZE];
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bios[0..4].copy_from_slice(&0xe321_f013_u32.to_le_bytes()); // MSR CPSR_c, #SVC (clear I)
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let mut bus = Memory::with_bios(vec![], bios).unwrap();
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pending_timer(&mut bus);
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let mut machine = Machine::new(Cpu::at_reset(), bus);
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assert!(machine.memory().irq_pending());
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().pc(), 4);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.cpu().registers()[14], 8);
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assert_eq!(machine.cpu().spsr(), Some(0x13));
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}
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#[test]
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fn ime_and_ie_gate_pending_device_requests_until_cpu_enables_them() {
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for register in [IE, IME] {
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let value = if register == IE { 8 } else { 1 };
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let mut machine = prepared(0xe580_1000, &[(0, register), (1, value)]); // STR r1, [r0]
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pending_timer(machine.memory_mut());
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machine.memory_mut().write16(register, 0).unwrap();
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assert!(!machine.memory().irq_pending());
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert!(machine.memory().irq_pending());
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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}
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}
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#[test]
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fn uncleared_request_reenters_after_irq_return_and_no_fiq_is_generated() {
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let bios = 0xe25e_f004_u32.to_le_bytes().repeat(BIOS_SIZE / 4); // SUBS pc, lr, #4
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let mut bus = Memory::with_bios(words(&[0xeaff_fffe]), bios).unwrap();
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pending_timer(&mut bus);
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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for _ in 0..3 {
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.cpu().mode(), Mode::Irq);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction); // I mask prevents immediate nesting
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assert_eq!(machine.cpu().mode(), Mode::System);
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assert_eq!(machine.cpu().pc(), ROM_START);
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}
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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}
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#[test]
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fn timer_irq_returns_to_thumb_without_skipping_the_interrupted_instruction() {
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let mut rom = words(&[0xe28f_0001, 0xe12f_ff10]); // ADD r0, pc, #1; BX r0
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rom.extend(0x2107_u16.to_le_bytes()); // MOV r1, #7 at offset 8
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let bios = 0xe25e_f004_u32.to_le_bytes().repeat(BIOS_SIZE / 4);
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let mut bus = Memory::with_bios(rom, bios).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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cpu.step(&mut bus).unwrap();
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cpu.step(&mut bus).unwrap();
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pending_timer(&mut bus);
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let mut machine = Machine::new(cpu, bus);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.cpu().spsr(), Some(0x3f));
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assert_eq!(machine.cpu().registers()[14], ROM_START + 12);
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machine.memory_mut().write16(IF, 8).unwrap();
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machine.step().unwrap();
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assert_eq!(machine.cpu().instruction_set(), InstructionSet::Thumb);
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assert_eq!(machine.cpu().pc(), ROM_START + 8);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[1], 7);
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assert_eq!(machine.cpu().pc(), ROM_START + 10);
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}
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#[test]
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fn diagnostics_do_not_advance_timers_or_clock() {
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for instruction in [0xf3a0_0001, 0xe590_1000] {
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// Unsupported or unmapped LDR
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let mut bus = Memory::new(words(&[instruction])).unwrap();
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timer(&mut bus);
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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let before = machine.cpu().clone();
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assert!(machine.step().is_err());
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), 0);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xffff);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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}
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}
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#[test]
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fn late_block_store_error_does_not_change_timer_reload_or_enable() {
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let mut machine = prepared(
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0xe8a0_003e,
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&[
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(0, TIMER_BASE),
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(1, 0x00c0_ffff),
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(2, 0x00c0_ffff),
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(3, 0x00c0_ffff),
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(4, 0x00c0_ffff),
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(5, 123),
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],
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); // STMIA r0!, {r1-r5}; fifth word is unmapped
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let before = machine.cpu().clone();
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assert!(machine.step().is_err());
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), 0);
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for index in 0..4 {
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let address = TIMER_BASE + index * 4;
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assert_eq!(machine.memory().read32(address).unwrap(), 0);
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machine.memory_mut().write16(address + 2, 0x80).unwrap();
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assert_eq!(machine.memory().read16(address).unwrap(), 0); // Hidden reload also unchanged
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}
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}
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#[test]
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fn late_block_store_error_does_not_acknowledge_if_or_modify_ie() {
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let mut machine = prepared(
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0xe8a0_001e,
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&[(0, IE), (1, 0x0008_ffff), (2, 123), (3, 1), (4, 42)],
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);
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// IE/IF, WAITCNT, IME are valid. The fourth word at 0x0400020c is not.
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pending_timer(machine.memory_mut());
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machine.memory_mut().write32(IME, 0).unwrap(); // Let the invalid store execute
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let before = machine.cpu().clone();
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let cycles = machine.cycles();
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assert!(machine.step().is_err());
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.memory().read32(IE).unwrap(), 0x0008_0008);
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assert_eq!(machine.memory().read32(WAITCNT).unwrap(), 0);
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assert_eq!(machine.memory().read32(IME).unwrap(), 0);
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assert_eq!(machine.last_timing().total(), 0);
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}
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#[test]
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fn late_block_load_error_preserves_cpu_and_devices() {
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let mut machine = prepared(0xe8b0_0006, &[(0, IME)]); // LDMIA r0!, {r1, r2}
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timer(machine.memory_mut());
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let before = machine.cpu().clone();
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assert!(machine.step().is_err());
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), 0);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xffff);
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}
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#[test]
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fn skipped_condition_charges_code_access_but_not_registers() {
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let mut bus = Memory::new(words(&[0x0280_0001])).unwrap(); // ADDEQ r0, r0, #1; Z clear
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timer(&mut bus);
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let mut machine = Machine::new(Cpu::new(ROM_START), bus);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[0], 0);
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assert_eq!(machine.cpu().pc(), ROM_START + 4);
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assert_eq!(machine.cycles(), 6);
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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}
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#[test]
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fn cpu_only_step_does_not_advance_device_time_or_deliver_irq() {
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let mut bus = Memory::new(words(&[0xe280_0001])).unwrap();
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pending_timer(&mut bus);
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let mut cpu = Cpu::new(ROM_START);
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let cycles = bus.cycles();
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers()[0], 1);
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assert_eq!(cpu.mode(), Mode::System);
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assert_eq!(bus.cycles(), cycles);
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assert!(bus.irq_pending());
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}
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