319 lines
9.5 KiB
Rust
319 lines
9.5 KiB
Rust
use std::{error::Error, fmt};
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use crate::memory::{Memory, MemoryError};
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// Semantic tests compare architectural state after successful instructions.
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// Error/rollback tests keep full Cpu equality, including buffered fetch results.
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#[cfg(test)]
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macro_rules! assert_cpu_arch_eq {
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($actual:expr, $expected:expr $(, $($message:tt)+)?) => {{
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let mut actual = $actual.clone();
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let mut expected = $expected.clone();
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actual.invalidate_pipeline();
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expected.invalidate_pipeline();
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assert_eq!(actual, expected $(, $($message)+)?);
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}};
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}
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mod alu;
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mod arm;
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mod exception;
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mod pipeline;
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mod status;
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mod thumb;
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mod timing;
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pub use exception::Exception;
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pub use status::Mode;
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mod transfer;
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#[cfg(test)]
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mod arm_pipeline_tests;
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#[cfg(test)]
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mod bios_access_tests;
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#[cfg(test)]
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mod compare_psr_tests;
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#[cfg(test)]
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mod dma_resume_tests;
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#[cfg(test)]
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mod exception_tests;
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#[cfg(test)]
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mod fetch_boundary_tests;
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#[cfg(test)]
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mod fetch_history_tests;
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#[cfg(test)]
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mod instruction_tests;
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#[cfg(test)]
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mod iwram_dma_tests;
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#[cfg(test)]
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mod iwram_open_bus_tests;
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#[cfg(test)]
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mod iwram_refill_tests;
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#[cfg(test)]
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mod load_alias_tests;
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#[cfg(test)]
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mod open_bus_tests;
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#[cfg(test)]
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mod status_tests;
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#[cfg(test)]
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mod tests;
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#[cfg(test)]
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mod thumb_empty_tests;
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#[cfg(test)]
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mod thumb_open_bus_tests;
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#[cfg(test)]
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mod thumb_pipeline_tests;
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#[cfg(test)]
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mod thumb_tests;
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#[cfg(test)]
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mod timing_tests;
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#[cfg(test)]
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mod transfer_tests;
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#[derive(Debug, Clone, PartialEq, Eq)]
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pub enum CpuError {
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Memory(MemoryError),
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UnsupportedInstruction { address: u32, instruction: u32 },
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UnsupportedThumbInstruction { address: u32, instruction: u16 },
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}
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impl fmt::Display for CpuError {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match self {
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Self::Memory(error) => write!(f, "{error}"),
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Self::UnsupportedThumbInstruction {
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address,
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instruction,
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} => {
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write!(
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f,
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"unsupported Thumb instruction {instruction:#06x} at {address:#010x}"
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)
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}
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Self::UnsupportedInstruction {
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address,
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instruction,
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} => {
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write!(
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f,
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"unsupported instruction {instruction:#010x} at {address:#010x}"
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)
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}
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}
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}
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}
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impl Error for CpuError {
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fn source(&self) -> Option<&(dyn Error + 'static)> {
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match self {
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Self::Memory(error) => Some(error),
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Self::UnsupportedInstruction { .. } | Self::UnsupportedThumbInstruction { .. } => None,
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}
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}
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}
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impl From<MemoryError> for CpuError {
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fn from(error: MemoryError) -> Self {
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Self::Memory(error)
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}
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}
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/// Arithmetic status flags from the current program status register.
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub struct Flags {
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pub negative: bool,
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pub zero: bool,
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/// For subtraction, carry means no unsigned borrow occurred.
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pub carry: bool,
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pub overflow: bool,
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}
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impl Flags {
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fn condition_passed(self, condition: u32) -> bool {
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match condition {
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0x0 => self.zero, // EQ
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0x1 => !self.zero, // NE
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0x2 => self.carry, // CS/HS
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0x3 => !self.carry, // CC/LO
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0x4 => self.negative, // MI
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0x5 => !self.negative, // PL
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0x6 => self.overflow, // VS
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0x7 => !self.overflow, // VC
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0x8 => self.carry && !self.zero, // HI
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0x9 => !self.carry || self.zero, // LS
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0xa => self.negative == self.overflow, // GE
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0xb => self.negative != self.overflow, // LT
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0xc => !self.zero && self.negative == self.overflow, // GT
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0xd => self.zero || self.negative != self.overflow, // LE
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0xe => true, // AL
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_ => false, // Reserved condition; rejected by Cpu::step.
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}
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}
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}
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/// Instruction encoding selected by the processor's T bit.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum InstructionSet {
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Arm,
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Thumb,
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}
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impl InstructionSet {
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pub(crate) fn width(self) -> u32 {
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match self {
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Self::Arm => 4,
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Self::Thumb => 2,
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}
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}
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fn align(self, address: u32) -> u32 {
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address & !(self.width() - 1)
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}
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}
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/// ARM/Thumb interpreter with register banks, instruction buffering, and nominal costs.
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/// Clone/equality include buffered fetch results and their instruction-set tag.
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#[derive(Debug, Clone, PartialEq, Eq)]
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pub struct Cpu {
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registers: [u32; 16],
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flags: Flags,
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instruction_set: InstructionSet,
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mode: Mode,
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irq_disabled: bool,
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fiq_disabled: bool,
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banks: status::Banks,
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pipeline: Option<pipeline::Pipeline>,
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}
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impl Cpu {
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/// Start directly at ARM-state test code in System mode, with interrupts enabled.
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/// This does not perform a GBA reset.
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pub fn new(entry_point: u32) -> Self {
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let mut registers = [0; 16];
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registers[15] = entry_point;
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Self {
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registers,
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flags: Flags::default(),
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instruction_set: InstructionSet::Arm,
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mode: Mode::System,
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irq_disabled: false,
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fiq_disabled: false,
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banks: status::Banks::default(),
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pipeline: None,
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}
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}
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/// r15 stores the next instruction address, not the pipeline-adjusted value.
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pub fn registers(&self) -> &[u32; 16] {
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&self.registers
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}
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pub fn pc(&self) -> u32 {
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self.registers[15]
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}
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pub fn flags(&self) -> Flags {
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self.flags
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}
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pub fn instruction_set(&self) -> InstructionSet {
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self.instruction_set
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}
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/// Execute one ARM instruction or one 16-bit Thumb instruction.
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/// Each half of a Thumb BL is a separate step.
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/// This CPU-only API does not execute DMA, advance clocks, or sample device interrupts.
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/// It records HALTCNT writes but does not enforce HALT. Use Machine::step for integration.
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/// Unsupported operations and memory errors leave CPU state unchanged.
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/// These errors are development diagnostics, not emulated CPU exceptions.
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pub fn step(&mut self, memory: &mut Memory) -> Result<(), CpuError> {
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let instruction = self.fetch(memory)?;
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self.execute_fetched(instruction, memory)
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}
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fn execute_fetched(
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&mut self,
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fetched: pipeline::Fetched,
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memory: &mut Memory,
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) -> Result<(), CpuError> {
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let pipeline::Fetched {
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instruction,
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continuation,
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lookahead,
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fill,
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} = fetched;
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// Record the executing instruction, not an operand's pipelined PC value.
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// Always clear the access context, including on diagnostic errors.
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let pc = self.pc();
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let instruction_set = self.instruction_set;
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let refill = self.instruction_refills(instruction);
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memory.begin_cpu_access(pc, self.instruction_set, fill.as_ref(), &lookahead);
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let result = self.execute_instruction(instruction, memory);
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memory.end_cpu_access(result.is_ok());
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if result.is_ok() {
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if refill {
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self.refill_pipeline(memory);
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} else {
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// A state change without an ordinary refill starts a cold sequence.
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self.pipeline = if self.instruction_set == instruction_set
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&& self.pc() == pc.wrapping_add(instruction_set.width())
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{
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Some(continuation)
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} else {
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None
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};
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}
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}
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result
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}
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fn execute_instruction(
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&mut self,
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instruction: u32,
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memory: &mut Memory,
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) -> Result<(), CpuError> {
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if self.instruction_set == InstructionSet::Thumb {
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return self.execute_thumb(instruction as u16, memory);
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}
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let condition = instruction >> 28;
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// Reserved in ARMv4. Do not decode ARMv5 unconditional extensions.
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if condition == 0xf {
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return Err(self.unsupported(instruction));
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}
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if !self.flags.condition_passed(condition) {
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self.registers[15] = self.pc().wrapping_add(4);
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return Ok(());
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}
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self.execute_arm(instruction, memory)
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}
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fn unsupported(&self, instruction: u32) -> CpuError {
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match self.instruction_set {
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InstructionSet::Arm => CpuError::UnsupportedInstruction {
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address: self.pc(),
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instruction,
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},
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InstructionSet::Thumb => CpuError::UnsupportedThumbInstruction {
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address: self.pc(),
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instruction: instruction as u16,
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},
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}
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}
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fn branch_exchange(&mut self, target: u32) {
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self.instruction_set = if target & 1 == 0 {
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InstructionSet::Arm
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} else {
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InstructionSet::Thumb
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};
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self.registers[15] = self.instruction_set.align(target);
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}
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fn operand_register(&self, register: usize, pc_offset: u32) -> u32 {
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if register == 15 {
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self.pc().wrapping_add(pc_offset)
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} else {
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self.registers[register]
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}
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}
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}
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