0xrsydn
|
f496f12ea3
|
feat(audio): add single-bank wave channel playback
|
2026-10-07 06:58:46 +07:00 |
|
0xrsydn
|
7546d17630
|
feat(serial): support disconnected Joybus configuration and local registers
|
2026-10-07 06:38:04 +07:00 |
|
0xrsydn
|
8b3b7ae62d
|
feat(cartridge): add explicit Flash identification and banked reads
|
2026-10-07 06:25:43 +07:00 |
|
0xrsydn
|
fce222eea2
|
feat(cartridge): implement RTC calendar transfers and clock updates
|
2026-10-07 05:59:29 +07:00 |
|
0xrsydn
|
692be36349
|
feat(cartridge): add explicit GPIO and RTC control support
|
2026-10-07 05:34:52 +07:00 |
|
0xrsydn
|
c5e19baed4
|
feat(serial): model disconnected multiplayer configuration
|
2026-10-07 05:06:49 +07:00 |
|
0xrsydn
|
0b36ef1e24
|
feat(serial): clock disconnected normal transfers and completion IRQs
|
2026-10-07 04:23:07 +07:00 |
|
0xrsydn
|
d329c76dc3
|
feat(serial): retain disconnected external-clock requests
|
2026-10-07 03:58:21 +07:00 |
|
0xrsydn
|
a0516de748
|
fix(memory): ignore emulated writes to mapped BIOS
|
2026-10-07 03:33:50 +07:00 |
|
0xrsydn
|
86f8663904
|
fix(serial): gate RCNT interrupt and Joybus controls by mode
|
2026-10-07 03:10:18 +07:00 |
|
0xrsydn
|
8ae7b3cf72
|
feat(audio): implement PSG noise channel 4
|
2026-10-07 02:54:57 +07:00 |
|
0xrsydn
|
aee3621513
|
feat(audio): implement PSG pulse channel 2
|
2026-10-07 02:33:41 +07:00 |
|
0xrsydn
|
9a646651da
|
feat(audio): implement PSG pulse channel 1
|
2026-10-07 01:58:08 +07:00 |
|
0xrsydn
|
5888c4d292
|
feat(audio): implement nominal Direct Sound playback and FIFO DMA
|
2026-10-07 01:40:51 +07:00 |
|
0xrsydn
|
d6a47a3e12
|
feat(bios): support sound and serial register reset
|
2026-10-07 01:01:07 +07:00 |
|
