Commit graph

13 commits

Author SHA1 Message Date
0xrsydn
7546d17630 feat(serial): support disconnected Joybus configuration and local registers 2026-10-07 06:38:04 +07:00
0xrsydn
c5e19baed4 feat(serial): model disconnected multiplayer configuration 2026-10-07 05:06:49 +07:00
0xrsydn
0b36ef1e24 feat(serial): clock disconnected normal transfers and completion IRQs 2026-10-07 04:23:07 +07:00
0xrsydn
d329c76dc3 feat(serial): retain disconnected external-clock requests 2026-10-07 03:58:21 +07:00
0xrsydn
9a646651da feat(audio): implement PSG pulse channel 1 2026-10-07 01:58:08 +07:00
0xrsydn
5888c4d292 feat(audio): implement nominal Direct Sound playback and FIFO DMA 2026-10-07 01:40:51 +07:00
0xrsydn
cb2772cef8 feat(io): model disabled sound and disconnected serial state 2026-10-07 01:01:07 +07:00
0xrsydn
27806ccf9e fix(timers): retain shared free-running prescaler phase 2026-10-06 22:07:49 +07:00
0xrsydn
bfecc87e84 fix(timers): apply machine accesses at bus completion 2026-10-06 21:52:09 +07:00
0xrsydn
e72c643640 feat(dma): retain per-channel transfer data
Retain independent known data across DMA blocks. Duplicate mapped halfword sources and select the destination lane for blocked sources below work RAM. Keep cold history diagnostic, commit only successful units, and preserve separate CPU/BIOS history rules.

Add 13 original regressions and pinned source research. CPU resume ownership, general DMA open bus, and IWRAM DMA lane effects remain explicit limits.

Validated on Darwin arm64: 930 workspace and 861 core/demo tests in debug and release, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports match the previous results exactly.
2026-10-06 02:18:24 +07:00
0xrsydn
c836944c2e feat(power): implement keypad-wake STOP and BIOS Stop service
Separate Running, Halt, and Stop states. Complete the entering instruction before freezing CPU, DMA, timers, display, and externally supplied clock advances. Wake STOP through the live enabled keypad condition without creating a clock-off IF request.

Implement original ARM SWI 0x03, preserve caller state, and expose zero-cycle StopIdle plus stopped frame-runner results. Retain DMA state, timer phase, and captured frames across sleep. Document keypad-only wake and unverified oscillator/edge timing.

Add core, BIOS, and demo regression tests; preserve BIOS-only access and failed-store isolation. Validated on Darwin arm64 with debug/release workspace and core/demo suites, Clippy, rustdoc, ten native window smoke tests, and terminal demos.
2026-10-05 18:28:23 +07:00
0xrsydn
597b02881b feat(input): implement KEYCNT keypad interrupt control
Add a dependency-free keypad state machine in gba-core, map KEYCNT, latch IF bit 12, and wake HALT through the existing interrupt gates. Sample complete CPU/DMA control writes once so transient byte values cannot create false requests.

Document the mGBA-style polling policy and its unverified hardware retrigger limits. Cover every button-state/selection pair, register masks, repeated requests, byte/word writes, failed-store isolation, DMA priority, ARM/Thumb IRQ return, BIOS IntrWait, and retained BIOS reset state.

Follow the restructured workspace and modular documentation. Validated on Darwin arm64: workspace and core/demo tests pass in debug and release, with Clippy, rustdoc, ten native window smoke tests, and terminal demos passing.
2026-10-05 18:05:26 +07:00
0xrsydn
f8a0676748 refactor: split into gameboy-rust workspace with core, demos, and desktop crates
Move the emulator into crates/gba-core, the original demo programs into
crates/gba-demos, and the minifb frontend into crates/desktop. The binary
is now gameboy-rust. Imports change from gba_rust to gba_core/gba_demos;
no behavior changes.

gba-core has no dependencies. Its integration tests use gba-demos as a
development dependency.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
2026-10-05 16:09:46 +07:00
Renamed from src/io.rs (Browse further)