0xrsydn
|
2d7eb6e4eb
|
feat(cpu): account for source fetches in branch and IRQ refills
|
2026-10-06 16:37:30 +07:00 |
|
0xrsydn
|
0650b60908
|
feat(cpu): charge non-refill code at pipeline fetch addresses
|
2026-10-06 15:35:10 +07:00 |
|
0xrsydn
|
0a696ea3e7
|
feat(cpu): use actual fetch regions for boundary bus snapshots
|
2026-10-06 15:14:34 +07:00 |
|
0xrsydn
|
f2c532f8f6
|
feat(cpu): retain IWRAM bus history across execution states
|
2026-10-06 14:31:14 +07:00 |
|
0xrsydn
|
e630d7a0ea
|
refactor(cpu): share instruction fetch samples with bus history
|
2026-10-06 14:17:35 +07:00 |
|
0xrsydn
|
ea055270f4
|
feat(cpu): retain Thumb instruction pipeline halfwords
|
2026-10-06 04:14:56 +07:00 |
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