refactor: split into gameboy-rust workspace with core, demos, and desktop crates
Move the emulator into crates/gba-core, the original demo programs into crates/gba-demos, and the minifb frontend into crates/desktop. The binary is now gameboy-rust. Imports change from gba_rust to gba_core/gba_demos; no behavior changes. gba-core has no dependencies. Its integration tests use gba-demos as a development dependency. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
This commit is contained in:
0xrsydn
parent
a8944d1d5f
commit
f8a0676748
113 changed files with 304 additions and 282 deletions
705
crates/gba-core/src/memory.rs
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705
crates/gba-core/src/memory.rs
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@ -0,0 +1,705 @@
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use std::{cell::Cell, error::Error, fmt};
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use crate::{
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display::{DisplayPosition, CYCLES_PER_LINE, HBLANK_START, VISIBLE_LINES},
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dma::{DmaError, DMA_BASE, DMA_END},
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input::Buttons,
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io::{Io, HALTCNT, POSTFLG},
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timing::{bus_cycles, AccessKind, AccessWidth, DataTiming, StepTiming},
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video::{self, sprites::pipeline, Framebuffer, VideoError},
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};
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pub const ROM_START: u32 = 0x0800_0000;
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const ROM_CAPACITY: usize = 32 * 1024 * 1024;
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pub const BIOS_SIZE: usize = 16 * 1024;
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pub const PALETTE_START: u32 = 0x0500_0000;
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pub const VRAM_START: u32 = 0x0600_0000;
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pub const OAM_START: u32 = 0x0700_0000;
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const VRAM_SIZE: usize = 96 * 1024;
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#[derive(Debug, Clone, PartialEq, Eq)]
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pub enum MemoryError {
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Unmapped(u32),
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ReadOnly(u32),
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Unaligned(u32),
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RomTooLarge(usize),
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InvalidBiosSize(usize),
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UnsupportedStop,
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}
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impl fmt::Display for MemoryError {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match self {
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Self::UnsupportedStop => write!(f, "HALTCNT STOP mode is not implemented"),
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Self::Unmapped(address) => write!(f, "unmapped memory at {address:#010x}"),
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Self::ReadOnly(address) => write!(f, "read-only memory at {address:#010x}"),
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Self::Unaligned(address) => write!(f, "unaligned memory access at {address:#010x}"),
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Self::RomTooLarge(size) => write!(f, "ROM size {size} exceeds 32 MiB"),
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Self::InvalidBiosSize(size) => {
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write!(f, "BIOS size {size} must be exactly {BIOS_SIZE} bytes")
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}
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}
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}
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}
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impl Error for MemoryError {}
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fn vram_index(address: u32) -> usize {
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let offset = (address & 0x1ffff) as usize;
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if offset >= 0x18000 {
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offset - 0x8000
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} else {
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offset
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}
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}
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/// Work/video/palette RAM, OAM, cartridge ROM, optional BIOS, and supported I/O.
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/// BIOS read protection and open-bus behavior are not modeled.
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pub struct Memory {
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external_ram: Vec<u8>,
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internal_ram: Vec<u8>,
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palette_ram: Vec<u8>,
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video_ram: Vec<u8>,
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oam: Vec<u8>,
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rom: Vec<u8>,
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bios: Option<Vec<u8>>,
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io: Io,
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cycles: u64,
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data_timing: Cell<Option<DataTiming>>,
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cpu_access: Option<u32>,
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scanline_capture: Option<video::capture::Capture>,
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sprite_pipeline: pipeline::SpritePipeline,
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}
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impl Memory {
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pub fn new(rom: Vec<u8>) -> Result<Self, MemoryError> {
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if rom.len() > ROM_CAPACITY {
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return Err(MemoryError::RomTooLarge(rom.len()));
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}
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Ok(Self {
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external_ram: vec![0; 256 * 1024],
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internal_ram: vec![0; 32 * 1024],
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palette_ram: vec![0; 1024],
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video_ram: vec![0; VRAM_SIZE],
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oam: vec![0; 1024],
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rom,
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bios: None,
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io: Io::default(),
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cycles: 0,
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data_timing: Cell::new(None),
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cpu_access: None,
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scanline_capture: None,
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sprite_pipeline: pipeline::SpritePipeline::default(),
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})
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}
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/// Map a caller-supplied 16 KiB image at the ARM exception vectors.
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/// No Nintendo BIOS is included. The image is read-only and is not mirrored.
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pub fn with_bios(rom: Vec<u8>, bios: Vec<u8>) -> Result<Self, MemoryError> {
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if bios.len() != BIOS_SIZE {
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return Err(MemoryError::InvalidBiosSize(bios.len()));
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}
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let mut memory = Self::new(rom)?;
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memory.bios = Some(bios);
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Ok(memory)
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}
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/// Total supplied clock cycles, wrapping at u64::MAX. Reads/writes alone
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/// consume no cycles. Machine stepping or the caller must advance time.
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pub fn cycles(&self) -> u64 {
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self.cycles
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}
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/// Advance devices and optional row capture. Multiple unserviced DMA requests
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/// coalesce. No CPU or DMA work is executed by this method.
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pub fn advance_cycles(&mut self, cycles: u32) {
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if cycles != 0 && !self.sprite_pipeline.started {
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// Synthetic reset begins on row0, with no preceding row227 to prepare it.
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self.prepare_sprite_row(0);
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self.sprite_pipeline.started = true;
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}
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if self.scanline_capture.is_none() {
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let position = self.io.display_position();
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let phase =
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u32::from(position.scanline) * CYCLES_PER_LINE + u32::from(position.line_cycle);
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let mut advanced = 0;
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for (offset, row) in pipeline::latest_events(phase, cycles).into_iter().flatten() {
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self.io.advance(offset - advanced);
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self.prepare_sprite_row(row);
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advanced = offset;
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}
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self.io.advance(cycles - advanced);
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} else {
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// Split at display and sprite-preparation edges. CPU/DMA writes have
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// already committed before these nominal clocks; no per-access timing.
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let mut remaining = cycles;
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while remaining != 0 {
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let position = self.io.display_position();
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let cycle = u32::from(position.line_cycle);
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let display_edge = if cycle < HBLANK_START {
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HBLANK_START - cycle
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} else {
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CYCLES_PER_LINE - cycle
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};
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let until =
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display_edge.min(pipeline::next_event(position.scanline, position.line_cycle));
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let step = remaining.min(until);
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self.io.advance(step);
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remaining -= step;
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if step == until {
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let position = self.io.display_position();
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if u32::from(position.line_cycle) == pipeline::PREPARE_CYCLE {
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if let Some(row) = pipeline::target(position.scanline) {
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self.prepare_sprite_row(row);
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}
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} else if u32::from(position.line_cycle) == HBLANK_START
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&& u32::from(position.scanline) < VISIBLE_LINES
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{
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let row = usize::from(position.scanline);
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if self.scanline_capture.as_ref().unwrap().wants_row(row) {
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let mut settings = self.io.video_settings(true);
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settings.prepared_objects = Some(self.sprite_pipeline.row(row));
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let pixels = video::render_rows(
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settings,
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&self.video_ram,
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&self.palette_ram,
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&self.oam,
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row..row + 1,
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);
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self.scanline_capture.as_mut().unwrap().record(row, pixels);
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}
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} else if position.line_cycle == 0
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&& u32::from(position.scanline) == VISIBLE_LINES
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{
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self.scanline_capture
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.as_mut()
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.unwrap()
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.publish(position.vblanks);
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}
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}
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}
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}
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self.cycles = self.cycles.wrapping_add(u64::from(cycles));
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}
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fn prepare_sprite_row(&mut self, row: usize) {
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let settings = self.io.video_settings(true);
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let prepared = video::sprites::prepare(
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settings.control,
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settings.mosaic,
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settings.vertical_mosaic.map(|v| v.object),
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&self.oam,
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&self.video_ram,
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row..row + 1,
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);
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self.sprite_pipeline.store(row, prepared);
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}
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/// Enable row capture without changing clocks or hardware registers. Disabled
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/// by default to keep CPU-only tests and large clock batches inexpensive.
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/// Repeating the current setting preserves captured data. Disabling drops it.
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pub fn set_scanline_rendering(&mut self, enabled: bool) {
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if enabled && self.scanline_capture.is_none() {
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self.scanline_capture = Some(video::capture::Capture::default());
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} else if !enabled {
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self.scanline_capture = None;
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}
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}
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/// VBlank number of the latest full captured frame, including failed frames.
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/// None means capture is disabled or no full frame has reached VBlank yet.
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pub fn captured_vblank(&self) -> Option<u64> {
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self.scanline_capture
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.as_ref()
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.and_then(video::capture::Capture::vblank)
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}
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/// Copy the latest captured frame. False means no complete frame is available.
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/// Rendering errors are reported here, not as CPU/DMA failures. On errors or
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/// false, the output is unchanged. Presenting does not advance time or consume
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/// the frame. Writes after capture cannot change its pixels.
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pub fn present_frame(&self, output: &mut Framebuffer) -> Result<bool, VideoError> {
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match &self.scanline_capture {
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Some(capture) => capture.present(output),
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None => Ok(false),
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}
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}
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/// Execute at most one DMA unit. Validate before side effects, then advance
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/// device clocks with the CPU paused. Earlier units remain committed on error.
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pub(crate) fn step_dma(&mut self) -> Result<Option<(usize, StepTiming)>, DmaError> {
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let Some(transfer) = self.io.next_dma()? else {
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return Ok(None);
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};
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let channel = transfer.channel;
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if (POSTFLG..=POSTFLG + 3).contains(&transfer.destination) {
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return Err(DmaError::PowerControlDestination {
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channel,
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address: transfer.destination,
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});
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}
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if transfer.source < 0x0200_0000 {
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return Err(DmaError::UnsupportedSource {
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channel,
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address: transfer.source,
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});
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}
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if (DMA_BASE..=DMA_END).contains(&transfer.destination) {
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return Err(DmaError::RegisterDestination {
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channel,
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address: transfer.destination,
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});
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}
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let map_error = |error| DmaError::Memory { channel, error };
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// Reads have no side effects. A failed destination leaves the unit pending.
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let value = match transfer.width {
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AccessWidth::Halfword => {
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self.write_index::<2>(transfer.destination)
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.map_err(map_error)?;
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u32::from(self.read16(transfer.source).map_err(map_error)?)
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}
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AccessWidth::Word => {
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self.write_index::<4>(transfer.destination)
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.map_err(map_error)?;
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self.read32(transfer.source).map_err(map_error)?
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}
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AccessWidth::Byte => unreachable!("DMA is never byte-wide"),
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};
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let kind = if transfer.first {
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AccessKind::NonSequential
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} else {
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AccessKind::Sequential
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};
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let timing = StepTiming {
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code_cycles: 0,
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data_cycles: bus_cycles(self.waitcnt(), transfer.source, transfer.width, kind)
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+ bus_cycles(self.waitcnt(), transfer.destination, transfer.width, kind),
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internal_cycles: if transfer.first { 2 } else { 0 },
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idle_cycles: 0,
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};
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match transfer.width {
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AccessWidth::Halfword => self.write16(transfer.destination, value as u16),
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AccessWidth::Word => self.write32(transfer.destination, value),
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AccessWidth::Byte => unreachable!("DMA is never byte-wide"),
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}
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.map_err(map_error)?;
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// Keep this channel active during its cycles: another edge must not
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// queue a second block while the current block is still transferring.
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self.advance_cycles(timing.total());
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self.io.complete_dma_unit(channel);
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Ok(Some((channel, timing)))
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}
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/// Whether HALT is waiting for IE & IF to become nonzero.
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/// IME and the CPU's interrupt mask do not affect this state.
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pub fn halted(&self) -> bool {
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self.io.halted()
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}
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pub(crate) fn next_event_cycles(&self) -> u32 {
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self.io.next_event_cycles()
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}
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pub(crate) fn begin_cpu_access(&mut self, pc: u32) {
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debug_assert!(self.cpu_access.is_none());
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self.cpu_access = Some(pc);
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}
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pub(crate) fn end_cpu_access(&mut self) {
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self.cpu_access = None;
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}
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fn can_write_power_control(&self) -> bool {
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// Bare memory writes are host/debug setup. CPU code must execute in BIOS.
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self.cpu_access.is_none_or(|pc| pc < BIOS_SIZE as u32)
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}
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/// Current scanline position and frame/VBlank event counters.
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pub fn display_position(&self) -> DisplayPosition {
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self.io.display_position()
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}
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/// The GBA IRQ line after IE/IF/IME gating, before the CPU's interrupt mask.
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pub fn irq_pending(&self) -> bool {
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self.io.irq_pending()
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}
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/// Replace the current pressed-button state. This does not advance time.
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/// KEYCNT and keypad interrupts are not implemented yet.
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pub fn set_buttons(&mut self, buttons: Buttons) {
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self.io.set_buttons(buttons);
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}
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/// Render a Mode 0–5 snapshot. No emulated cycles are consumed.
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/// Uses programmed affine origins, geometric window bounds, and screen-grid mosaic.
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/// Ignores captured history. Use present_frame for latched scanline state.
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pub fn render_frame(&self, frame: &mut Framebuffer) -> Result<(), VideoError> {
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video::render(
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self.io.video_settings(false),
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&self.video_ram,
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&self.palette_ram,
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&self.oam,
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frame,
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)
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}
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/// Current Game Pak wait-state control. Prefetch is not implemented.
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pub fn waitcnt(&self) -> u16 {
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self.io.waitcnt()
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}
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pub(crate) fn begin_data_timing(&self) {
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debug_assert!(self.data_timing.get().is_none());
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self.data_timing.set(Some(DataTiming::default()));
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}
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pub(crate) fn end_data_timing(&self) -> u32 {
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self.data_timing.take().map_or(0, |trace| trace.cycles)
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}
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fn record_access(&self, address: u32, width: AccessWidth) {
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if let Some(mut trace) = self.data_timing.get() {
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trace.access(self.waitcnt(), address, width);
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self.data_timing.set(Some(trace));
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}
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}
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pub fn read8(&self, address: u32) -> Result<u8, MemoryError> {
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let value = self.read_byte(address)?;
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self.record_access(address, AccessWidth::Byte);
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Ok(value)
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}
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// Multi-byte reads use this helper to avoid charging each byte as a bus access.
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fn read_byte(&self, address: u32) -> Result<u8, MemoryError> {
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match address >> 24 {
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0x00 => self
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.bios
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.as_ref()
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.and_then(|bios| bios.get(address as usize))
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.copied()
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.ok_or(MemoryError::Unmapped(address)),
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0x02 => Ok(self.external_ram[(address & 0x3ffff) as usize]),
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0x03 => Ok(self.internal_ram[(address & 0x7fff) as usize]),
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0x04 => self.io.read8(address).ok_or(MemoryError::Unmapped(address)),
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0x05 => Ok(self.palette_ram[(address & 0x3ff) as usize]),
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0x06 => Ok(self.video_ram[vram_index(address)]),
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0x07 => Ok(self.oam[(address & 0x3ff) as usize]),
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0x08..=0x0d => self
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.rom
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.get((address & 0x01ff_ffff) as usize)
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.copied()
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.ok_or(MemoryError::Unmapped(address)),
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_ => Err(MemoryError::Unmapped(address)),
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}
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}
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pub fn write8(&mut self, address: u32, value: u8) -> Result<(), MemoryError> {
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self.write_aligned(address, [value])
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}
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pub fn write16(&mut self, address: u32, value: u16) -> Result<(), MemoryError> {
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self.write_aligned(address, value.to_le_bytes())
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}
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pub fn write32(&mut self, address: u32, value: u32) -> Result<(), MemoryError> {
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self.write_aligned(address, value.to_le_bytes())
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}
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|
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// Validate the complete access before any RAM or I/O side effects.
|
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// Timer reload bytes precede control bytes in a combined 32-bit write.
|
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fn write_aligned<const N: usize>(
|
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&mut self,
|
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address: u32,
|
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bytes: [u8; N],
|
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) -> Result<(), MemoryError> {
|
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let index = self.validate_write(address, &bytes)?;
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self.record_access(
|
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address,
|
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match N {
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1 => AccessWidth::Byte,
|
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2 => AccessWidth::Halfword,
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4 => AccessWidth::Word,
|
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_ => unreachable!("unsupported bus width"),
|
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},
|
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);
|
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if address >> 24 == 0x04 {
|
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for (offset, byte) in bytes.into_iter().enumerate() {
|
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let byte_address = address + offset as u32;
|
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if matches!(byte_address, POSTFLG | HALTCNT) && !self.can_write_power_control() {
|
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continue; // BIOS-only CPU writes; ignored elsewhere, including STOP requests.
|
||||
}
|
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self.io.write8(byte_address, byte);
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}
|
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return Ok(());
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}
|
||||
if N == 1 && address >> 24 == 0x07 {
|
||||
return Ok(()); // OAM ignores byte writes; halfword/word writes remain valid.
|
||||
}
|
||||
if N == 1 && matches!(address >> 24, 0x05 | 0x06) {
|
||||
let bg_limit = if (3..=5).contains(&(self.io.display_control() & 7)) {
|
||||
0x14000
|
||||
} else {
|
||||
0x10000
|
||||
};
|
||||
// Byte writes to OBJ VRAM are ignored. BG/palette writes duplicate
|
||||
// the byte into both halves of the aligned 16-bit location.
|
||||
if address >> 24 == 0x06 && index >= bg_limit {
|
||||
return Ok(());
|
||||
}
|
||||
let ram = if address >> 24 == 0x05 {
|
||||
&mut self.palette_ram
|
||||
} else {
|
||||
&mut self.video_ram
|
||||
};
|
||||
let aligned = index & !1;
|
||||
ram[aligned..aligned + 2].fill(bytes[0]);
|
||||
return Ok(());
|
||||
}
|
||||
let ram = match address >> 24 {
|
||||
0x02 => &mut self.external_ram,
|
||||
0x03 => &mut self.internal_ram,
|
||||
0x05 => &mut self.palette_ram,
|
||||
0x06 => &mut self.video_ram,
|
||||
0x07 => &mut self.oam,
|
||||
_ => unreachable!("validated writable region"),
|
||||
};
|
||||
ram[index..index + N].copy_from_slice(&bytes);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn validate_write<const N: usize>(
|
||||
&self,
|
||||
address: u32,
|
||||
bytes: &[u8; N],
|
||||
) -> Result<usize, MemoryError> {
|
||||
let index = self.write_index::<N>(address)?;
|
||||
if self.can_write_power_control() {
|
||||
for (offset, byte) in bytes.iter().enumerate() {
|
||||
if address + offset as u32 == HALTCNT && byte & 0x80 != 0 {
|
||||
return Err(MemoryError::UnsupportedStop);
|
||||
}
|
||||
}
|
||||
}
|
||||
Ok(index)
|
||||
}
|
||||
|
||||
fn write_index<const N: usize>(&self, address: u32) -> Result<usize, MemoryError> {
|
||||
if address & (N as u32 - 1) != 0 {
|
||||
return Err(MemoryError::Unaligned(address));
|
||||
}
|
||||
match address >> 24 {
|
||||
0x00 if self.bios.is_some() && address < BIOS_SIZE as u32 => {
|
||||
Err(MemoryError::ReadOnly(address))
|
||||
}
|
||||
0x02 => Ok((address & 0x3ffff) as usize),
|
||||
0x03 => Ok((address & 0x7fff) as usize),
|
||||
0x05 => Ok((address & 0x3ff) as usize),
|
||||
0x06 => Ok(vram_index(address)),
|
||||
0x07 => Ok((address & 0x3ff) as usize),
|
||||
0x04 => {
|
||||
for offset in 0..N as u32 {
|
||||
if !Io::mapped(address + offset) {
|
||||
return Err(MemoryError::Unmapped(address + offset));
|
||||
}
|
||||
}
|
||||
Ok(0) // I/O does not use a RAM index.
|
||||
}
|
||||
0x08..=0x0d => Err(MemoryError::ReadOnly(address)),
|
||||
_ => Err(MemoryError::Unmapped(address)),
|
||||
}
|
||||
}
|
||||
|
||||
/// Validate a batch before any RAM or I/O writes. Diagnostic errors cannot
|
||||
/// leave a partial block store. This is not a model of hardware data aborts.
|
||||
/// Mapped I/O reads currently have no side effects; writes cannot fail after validation.
|
||||
pub(crate) fn write_words(&mut self, writes: &[(u32, u32)]) -> Result<(), MemoryError> {
|
||||
for &(address, value) in writes {
|
||||
self.validate_write(address, &value.to_le_bytes())?;
|
||||
}
|
||||
for &(address, value) in writes {
|
||||
// The map cannot change between validation and these writes.
|
||||
self.write32(address, value)?;
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn read16(&self, address: u32) -> Result<u16, MemoryError> {
|
||||
if address & 1 != 0 {
|
||||
return Err(MemoryError::Unaligned(address));
|
||||
}
|
||||
let value = u16::from_le_bytes([self.read_byte(address)?, self.read_byte(address + 1)?]);
|
||||
self.record_access(address, AccessWidth::Halfword);
|
||||
Ok(value)
|
||||
}
|
||||
|
||||
/// The bus requires alignment; the CPU applies ARM7TDMI load rotation.
|
||||
pub fn read32(&self, address: u32) -> Result<u32, MemoryError> {
|
||||
if address & 3 != 0 {
|
||||
return Err(MemoryError::Unaligned(address));
|
||||
}
|
||||
let value = u32::from_le_bytes([
|
||||
self.read_byte(address)?,
|
||||
self.read_byte(address + 1)?,
|
||||
self.read_byte(address + 2)?,
|
||||
self.read_byte(address + 3)?,
|
||||
]);
|
||||
self.record_access(address, AccessWidth::Word);
|
||||
Ok(value)
|
||||
}
|
||||
}
|
||||
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use super::*;
|
||||
use crate::{
|
||||
display::CYCLES_PER_LINE,
|
||||
io::{DISPSTAT, IF},
|
||||
};
|
||||
|
||||
#[test]
|
||||
fn affine_state_tracks_without_capture_and_survives_failed_batch_writes() {
|
||||
use crate::io::{BG2PA, BG2PB, BG2PD, BG2X, DISPCNT};
|
||||
let mut bulk = Memory::new(vec![]).unwrap();
|
||||
let mut captured = Memory::new(vec![]).unwrap();
|
||||
captured.set_scanline_rendering(true);
|
||||
for m in [&mut bulk, &mut captured] {
|
||||
m.write16(DISPCNT, 0x403).unwrap();
|
||||
m.write16(BG2PA, 256).unwrap();
|
||||
m.write16(BG2PB, (-181i16) as u16).unwrap();
|
||||
m.write16(BG2PD, 91).unwrap();
|
||||
m.write32(BG2X, 12345).unwrap();
|
||||
}
|
||||
for cycles in [0, 1006, 226, 7319, 280896, 1232 * 317] {
|
||||
for m in [&mut bulk, &mut captured] {
|
||||
m.advance_cycles(cycles);
|
||||
}
|
||||
assert_eq!(
|
||||
bulk.io.video_settings(true).backgrounds[2].affine,
|
||||
captured.io.video_settings(true).backgrounds[2].affine
|
||||
);
|
||||
}
|
||||
let before = bulk.io.video_settings(true).backgrounds[2].affine;
|
||||
assert!(bulk.write_words(&[(BG2X, 0), (0x0400_0058, 0)]).is_err());
|
||||
assert_eq!(bulk.io.video_settings(true).backgrounds[2].affine, before);
|
||||
bulk.set_scanline_rendering(true);
|
||||
bulk.set_scanline_rendering(false);
|
||||
assert_eq!(bulk.io.video_settings(true).backgrounds[2].affine, before);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn window_flags_match_batched_and_captured_clocks_and_survive_failed_writes() {
|
||||
use crate::io::{WIN0V, WIN1V};
|
||||
let mut bulk = Memory::new(vec![]).unwrap();
|
||||
let mut captured = Memory::new(vec![]).unwrap();
|
||||
captured.set_scanline_rendering(true);
|
||||
for (cycles, first, second) in [
|
||||
(1006, 0x0010, 0xc808),
|
||||
(226, 0x0010, 0xc808),
|
||||
(1232 * 5, 0x0508, 0x0014),
|
||||
(280896 * 3, 0xffff, 0xc808),
|
||||
(1232 * 500 + 100, 0x00ff, 0xff00),
|
||||
] {
|
||||
for m in [&mut bulk, &mut captured] {
|
||||
m.write16(WIN0V, first).unwrap();
|
||||
m.write16(WIN1V, second).unwrap();
|
||||
m.advance_cycles(cycles);
|
||||
}
|
||||
assert_eq!(
|
||||
bulk.io.video_settings(true).vertical_windows,
|
||||
captured.io.video_settings(true).vertical_windows
|
||||
);
|
||||
}
|
||||
let before = bulk.io.clone();
|
||||
assert!(bulk.write_words(&[(WIN0V, 0), (0x0400_0058, 0)]).is_err());
|
||||
assert_eq!(bulk.io, before);
|
||||
bulk.set_scanline_rendering(true);
|
||||
bulk.set_scanline_rendering(false);
|
||||
assert_eq!(bulk.io, before);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn mosaic_phase_matches_batched_capture_and_survives_writes_and_capture_toggles() {
|
||||
use crate::io::{BG2CNT, BG2PD, DISPCNT, MOSAIC};
|
||||
let mut bulk = Memory::new(vec![]).unwrap();
|
||||
let mut captured = Memory::new(vec![]).unwrap();
|
||||
captured.set_scanline_rendering(true);
|
||||
for m in [&mut bulk, &mut captured] {
|
||||
m.write16(DISPCNT, 0x403).unwrap();
|
||||
m.write16(BG2CNT, 0x40).unwrap();
|
||||
m.write16(BG2PD, 91).unwrap();
|
||||
}
|
||||
for (cycles, sizes) in [
|
||||
(6 * CYCLES_PER_LINE, 0x7070),
|
||||
(9 * CYCLES_PER_LINE, 0x1010),
|
||||
(1006, 0x3010),
|
||||
(226, 0x0030),
|
||||
(280896 * 3 + 1232 * 5, 0x9030),
|
||||
] {
|
||||
for m in [&mut bulk, &mut captured] {
|
||||
m.write16(MOSAIC, sizes).unwrap();
|
||||
m.advance_cycles(cycles);
|
||||
}
|
||||
assert_eq!(bulk.io, captured.io);
|
||||
}
|
||||
let before = bulk.io.clone();
|
||||
assert!(bulk.write_words(&[(MOSAIC, 0), (0x0400_0058, 0)]).is_err());
|
||||
assert_eq!(bulk.io, before);
|
||||
bulk.set_scanline_rendering(true);
|
||||
bulk.set_scanline_rendering(false);
|
||||
assert_eq!(bulk.io, before);
|
||||
let counters = bulk.io.video_settings(true).vertical_mosaic;
|
||||
bulk.write16(MOSAIC, 0).unwrap();
|
||||
bulk.advance_cycles(0);
|
||||
assert_eq!(bulk.io.video_settings(true).vertical_mosaic, counters);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn horizontal_history_matches_capture_clock_splits_and_survives_failed_writes() {
|
||||
use crate::io::WIN0H;
|
||||
let mut bulk = Memory::new(vec![]).unwrap();
|
||||
let mut captured = Memory::new(vec![]).unwrap();
|
||||
captured.set_scanline_rendering(true);
|
||||
for (cycles, bounds) in [
|
||||
(81, 0x0a50),
|
||||
(3, 0x1450),
|
||||
(922, 0x2828),
|
||||
(14, 0xff0a),
|
||||
(1, 0xff0a),
|
||||
(211, 0xff0a),
|
||||
(280896 * 3 + 100, 0xf014),
|
||||
] {
|
||||
for m in [&mut bulk, &mut captured] {
|
||||
m.write32(WIN0H, bounds | ((bounds ^ 0x371b) << 16))
|
||||
.unwrap();
|
||||
m.advance_cycles(cycles);
|
||||
}
|
||||
assert_eq!(bulk.io, captured.io);
|
||||
}
|
||||
let before = bulk.io.clone();
|
||||
assert!(bulk.write_words(&[(WIN0H, 0), (0x0400_0058, 0)]).is_err());
|
||||
assert_eq!(bulk.io, before);
|
||||
bulk.advance_cycles(0);
|
||||
bulk.set_scanline_rendering(true);
|
||||
bulk.set_scanline_rendering(false);
|
||||
let mut snapshot = Framebuffer::default();
|
||||
bulk.render_frame(&mut snapshot).unwrap();
|
||||
assert_eq!(bulk.io, before);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn failed_batch_does_not_change_comparison_or_latch_match_irq() {
|
||||
let mut bus = Memory::new(vec![]).unwrap();
|
||||
bus.advance_cycles(7 * CYCLES_PER_LINE);
|
||||
let before = bus.display_position();
|
||||
// This batch is no longer reachable with one CPU STM: the mapped
|
||||
// display register area now exceeds its sixteen-word transfer limit.
|
||||
assert_eq!(
|
||||
bus.write_words(&[(DISPSTAT, 0x720), (0x0400_0058, 0)]),
|
||||
Err(MemoryError::Unmapped(0x0400_0058))
|
||||
);
|
||||
assert_eq!(bus.display_position(), before);
|
||||
assert_eq!(bus.read16(DISPSTAT).unwrap(), 0);
|
||||
assert_eq!(bus.read16(IF).unwrap(), 0);
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue