feat(cpu): retain IWRAM bus history across execution states

docs/hardware/dma.md

@@ -58,10 +58,12 @@ DMA writes to DMA registers return `DmaError::RegisterDestination`; self-modifyi
 Other accesses use the existing memory map, alignment checks, mirrors, and I/O write rules.
 Other unmapped reads and cartridge writes remain diagnostics, not general DMA open-bus behavior.
 A failed unit changes no memory, device state, or clock. Earlier units remain committed; the failed unit remains pending.
-Successful units update existing Thumb IWRAM continuation lanes for their actual IWRAM reads and writes, in that order.
+Successful units update local IWRAM lanes for their actual IWRAM reads and writes, in that order.
+No CPU continuation is required; DMA can establish lanes before the first CPU instruction.
 Accesses elsewhere leave those local lanes unchanged. Failed units preserve history.
-The resumed CPU's PC+4 fetch then updates its addressed halfword. No universal DMA-value override is used.
-See [bounded IWRAM DMA history](cpu.md#dma-effects-on-thumb-iwram-continuations) for the scope.
+A resumed Thumb PC+4 fetch updates its addressed halfword; a cold pipeline fill drives all its new samples.
+No universal DMA-value override is used.
+See [local IWRAM DMA history](cpu.md#dma-effects-on-thumb-iwram-continuations) for the scope.
 
 ## Retained channel data
 
@@ -88,5 +90,5 @@ Earlier successful units remain committed. Normal destination validation, nomina
 This error policy is not a model of hardware data aborts.
 
 See [the latch evidence and scope](../research/dma-data-latches.md).
-General DMA open-bus reads, cross-state IWRAM history, and sub-instruction bus ownership remain unimplemented.
+General DMA open-bus reads and sub-instruction bus ownership remain unimplemented.
 In particular, the known channel value does not supply unused/write-only I/O reads or CPU open-bus snapshots.