feat(dma): retain per-channel transfer data

Retain independent known data across DMA blocks. Duplicate mapped halfword sources and select the destination lane for blocked sources below work RAM. Keep cold history diagnostic, commit only successful units, and preserve separate CPU/BIOS history rules.

Add 13 original regressions and pinned source research. CPU resume ownership, general DMA open bus, and IWRAM DMA lane effects remain explicit limits.

Validated on Darwin arm64: 930 workspace and 861 core/demo tests in debug and release, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports match the previous results exactly.

crates/gba-core/tests/dma.rs

@@ -8,6 +8,9 @@ use gba_core::{
     timing::{bus_cycles, AccessKind, AccessWidth},
 };
 
+#[path = "dma/latch.rs"]
+mod latch;
+
 const SOURCE: u32 = 0x0200_0000;
 const DEST: u32 = 0x0300_0000;