feat(dma): retain per-channel transfer data
Retain independent known data across DMA blocks. Duplicate mapped halfword sources and select the destination lane for blocked sources below work RAM. Keep cold history diagnostic, commit only successful units, and preserve separate CPU/BIOS history rules. Add 13 original regressions and pinned source research. CPU resume ownership, general DMA open bus, and IWRAM DMA lane effects remain explicit limits. Validated on Darwin arm64: 930 workspace and 861 core/demo tests in debug and release, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports match the previous results exactly.
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0xrsydn
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12 changed files with 465 additions and 24 deletions
297
crates/gba-core/tests/dma/latch.rs
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297
crates/gba-core/tests/dma/latch.rs
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@ -0,0 +1,297 @@
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//! Original tests of per-channel retained data, not CPU open-bus handoff.
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use super::*;
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const DATA: u32 = 0x9a73_b5e1;
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const OTHER: u32 = 0x2468_1357;
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fn seed(machine: &mut Machine, channel: usize, value: u32) {
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machine.memory_mut().write32(SOURCE, value).unwrap();
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configure(machine.memory_mut(), channel, SOURCE, DEST, 1, 0x400);
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units(machine, channel, 1);
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}
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fn blocked(machine: &mut Machine, channel: usize, destination: u32, control: u16) {
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configure(machine.memory_mut(), channel, 0, destination, 1, control);
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units(machine, channel, 1);
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}
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#[test]
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fn blocked_sources_reuse_each_channels_word_without_reading_bios() {
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for channel in 0..4 {
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for source in [0, 0x3ffc, 0x4000, 0x0100_0000, 0x01ff_fffc] {
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let mut bios = vec![0x62; BIOS_SIZE];
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bios[..4].copy_from_slice(&OTHER.to_le_bytes());
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let mut machine = Machine::new(
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Cpu::new(ROM_START),
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Memory::with_bios(words(&[0xeaff_fffe]), bios).unwrap(),
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);
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seed(&mut machine, channel, DATA);
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machine.memory_mut().write32(SOURCE, 0).unwrap();
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assert_eq!(machine.memory().read32(0).unwrap(), OTHER);
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configure(machine.memory_mut(), channel, source, DEST + 4, 1, 0x400);
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units(&mut machine, channel, 1);
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assert_eq!(machine.memory().read32(DEST + 4).unwrap(), DATA);
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assert!(!enabled(&machine, channel));
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}
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}
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}
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#[test]
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fn blocked_halfwords_select_destination_lane_and_do_not_duplicate_retained_word() {
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for channel in 0..4 {
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let mut machine = machine();
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seed(&mut machine, channel, DATA);
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// Neither source alignment nor halfword width may replace the old full word.
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for source in [0, 2, 0x3ffe, 0x01ff_fffe] {
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for lane in [0, 2] {
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configure(machine.memory_mut(), channel, source, DEST + 4 + lane, 1, 0);
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units(&mut machine, channel, 1);
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}
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assert_eq!(machine.memory().read32(DEST + 4).unwrap(), DATA);
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}
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blocked(&mut machine, channel, DEST + 8, 0x400);
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assert_eq!(machine.memory().read32(DEST + 8).unwrap(), DATA);
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}
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}
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#[test]
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fn mapped_halfword_sources_duplicate_either_source_lane_in_the_channel_latch() {
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for channel in 0..4 {
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for source_lane in [0, 2] {
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for destination_lane in [0, 2] {
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let mut machine = machine();
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seed(&mut machine, channel, OTHER);
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machine.memory_mut().write32(SOURCE, DATA).unwrap();
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configure(
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machine.memory_mut(),
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channel,
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SOURCE + source_lane,
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DEST + destination_lane,
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1,
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0,
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);
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units(&mut machine, channel, 1);
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let half = (DATA >> (source_lane * 8)) as u16;
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assert_eq!(
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machine.memory().read16(DEST + destination_lane).unwrap(),
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half
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);
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blocked(&mut machine, channel, DEST + 4, 0x400);
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assert_eq!(
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machine.memory().read32(DEST + 4).unwrap(),
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u32::from(half) * 0x10001
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);
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}
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}
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}
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}
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#[test]
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fn latches_are_independent_and_survive_completion_disable_and_host_access() {
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let mut machine = machine();
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for channel in 0..4 {
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seed(&mut machine, channel, DATA ^ (0x1111_1111 * channel as u32));
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}
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machine.memory_mut().write32(SOURCE, OTHER).unwrap();
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assert_eq!(machine.memory().read32(SOURCE).unwrap(), OTHER);
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for channel in (0..4).rev() {
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machine.memory_mut().write16(base(channel) + 10, 0).unwrap();
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blocked(&mut machine, channel, DEST + channel as u32 * 4, 0x400);
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assert_eq!(
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machine.memory().read32(DEST + channel as u32 * 4).unwrap(),
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DATA ^ (0x1111_1111 * channel as u32)
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);
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}
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}
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#[test]
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fn cold_channel_stays_unknown_despite_other_channels_and_host_reads() {
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for channel in 0..4 {
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let mut machine = machine();
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seed(&mut machine, (channel + 1) % 4, DATA);
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assert_eq!(machine.memory().read32(DEST).unwrap(), DATA);
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configure(machine.memory_mut(), channel, 0, DEST + 4, 1, 0x4400);
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let cycles = machine.cycles();
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let timing = machine.last_timing();
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let cpu = machine.cpu().clone();
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for _ in 0..2 {
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assert_eq!(
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machine.step(),
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Err(MachineError::Dma(DmaError::UnsupportedSource {
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channel,
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address: 0
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}))
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);
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assert_eq!(machine.cpu(), &cpu);
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.last_timing(), timing);
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assert_eq!(machine.memory().read32(DEST + 4).unwrap(), 0);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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assert!(enabled(&machine, channel));
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}
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}
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}
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#[test]
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fn zero_is_known_data_not_an_unknown_latch() {
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let mut machine = machine();
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seed(&mut machine, 3, 0);
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machine.memory_mut().write32(DEST + 4, u32::MAX).unwrap();
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blocked(&mut machine, 3, DEST + 4, 0x400);
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assert_eq!(machine.memory().read32(DEST + 4).unwrap(), 0);
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}
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#[test]
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fn failed_units_preserve_the_old_latch_without_new_data_or_irq() {
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for (source, destination, control) in [
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(0x0e00_0000, DEST, 0x4400), // Unmapped reads do not use a known latch.
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(SOURCE, ROM_START, 0x4400),
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(SOURCE, 0x0400_0058, 0x4400),
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(SOURCE, DMA_BASE, 0x4400),
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(SOURCE, 0x0400_0300, 0x4400),
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(SOURCE, DEST, 0x4580), // Unsupported source mode.
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(0, ROM_START, 0x4400), // A blocked source cannot bypass destination checks.
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] {
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let mut machine = machine();
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seed(&mut machine, 3, DATA);
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machine.memory_mut().write32(SOURCE, OTHER).unwrap();
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configure(machine.memory_mut(), 3, source, destination, 1, control);
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let cycles = machine.cycles();
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let timing = machine.last_timing();
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for _ in 0..2 {
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assert!(machine.step().is_err());
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.last_timing(), timing);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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assert_eq!(machine.memory().read32(DEST).unwrap(), DATA);
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}
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machine.memory_mut().write16(base(3) + 10, 0).unwrap();
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blocked(&mut machine, 3, DEST + 4, 0x400);
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assert_eq!(machine.memory().read32(DEST + 4).unwrap(), DATA);
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}
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}
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#[test]
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fn failed_destination_does_not_seed_a_cold_channel() {
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let mut machine = machine();
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machine.memory_mut().write32(SOURCE, DATA).unwrap();
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configure(machine.memory_mut(), 3, SOURCE, ROM_START, 1, 0x400);
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assert!(machine.step().is_err());
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machine.memory_mut().write16(base(3) + 10, 0).unwrap();
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configure(machine.memory_mut(), 3, 0, DEST, 1, 0x400);
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assert_eq!(
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machine.step(),
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Err(MachineError::Dma(DmaError::UnsupportedSource {
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channel: 3,
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address: 0
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}))
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);
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assert_eq!(machine.cycles(), 0);
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}
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#[test]
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fn source_counter_crossing_into_blocked_region_retains_the_last_completed_unit() {
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let mut machine = machine();
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machine.memory_mut().write32(SOURCE, DATA).unwrap();
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configure(machine.memory_mut(), 3, SOURCE, DEST, 3, 0x4480); // Decrement word source, IRQ.
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units(&mut machine, 3, 3);
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for offset in [0, 4, 8] {
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assert_eq!(machine.memory().read32(DEST + offset).unwrap(), DATA);
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}
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assert_eq!(machine.cycles(), 13); // 6+1+2, then two 1+1 units.
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assert_eq!(machine.memory().read16(IF).unwrap(), 1 << 11);
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assert!(!enabled(&machine, 3));
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}
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#[test]
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fn failed_later_read_retains_last_successful_halfword_not_partial_bytes() {
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let mut machine = Machine::new(
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Cpu::new(ROM_START),
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Memory::new(vec![0x37, 0x92, 0x6a]).unwrap(),
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);
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configure(machine.memory_mut(), 3, ROM_START, DEST, 2, 0);
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units(&mut machine, 3, 1);
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assert!(machine.step().is_err());
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machine.memory_mut().write16(base(3) + 10, 0).unwrap();
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blocked(&mut machine, 3, DEST + 4, 0x400);
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assert_eq!(machine.memory().read32(DEST + 4).unwrap(), 0x9237_9237);
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}
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#[test]
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fn cancellation_keeps_the_last_completed_unit_not_programmed_source_bytes() {
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let mut machine = machine();
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machine.memory_mut().write32(SOURCE, DATA).unwrap();
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machine.memory_mut().write32(SOURCE + 4, OTHER).unwrap();
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configure(machine.memory_mut(), 3, SOURCE, DEST, 3, 0x400);
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units(&mut machine, 3, 2);
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assert!(enabled(&machine, 3));
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machine.memory_mut().write16(base(3) + 10, 0).unwrap();
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machine.memory_mut().write32(SOURCE + 4, 0).unwrap();
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blocked(&mut machine, 3, DEST + 8, 0x400);
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assert_eq!(machine.memory().read32(DEST + 8).unwrap(), OTHER);
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}
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#[test]
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fn blocked_dma_does_not_read_or_replace_the_protected_cpu_bios_word() {
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let mut bios = vec![0; BIOS_SIZE];
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bios[..16].copy_from_slice(&words(&[
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0xe59f_0000, // LDR r0,[pc]: ROM destination.
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0xe12f_ff10, // BX r0: retained BIOS word comes from address 12.
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ROM_START,
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OTHER,
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]));
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let mut machine = Machine::new(
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Cpu::new(0),
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Memory::with_bios(words(&[0xe592_1000, 0xeaff_fffe, 0]), bios).unwrap(),
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); // ROM LDR r1,[r2], with r2=0.
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for _ in 0..2 {
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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}
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seed(&mut machine, 3, DATA);
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blocked(&mut machine, 3, DEST + 4, 0x400);
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assert_eq!(machine.memory().read32(DEST + 4).unwrap(), DATA);
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assert_eq!(machine.memory().read32(0).unwrap(), 0xe59f_0000);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[1], OTHER);
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}
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#[test]
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fn repeated_hblank_blocks_and_priority_keep_channel_history_and_nominal_clocks() {
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let mut machine = machine();
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seed(&mut machine, 0, OTHER);
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seed(&mut machine, 3, DATA);
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machine
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.memory_mut()
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.write32(TIMER_BASE, 0x0080_0000)
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.unwrap();
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let start = machine.cycles();
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for channel in [3, 0] {
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configure(
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machine.memory_mut(),
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channel,
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0,
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DEST + 8 + channel as u32 * 8,
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1,
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0x6340,
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);
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} // Halfword, fixed source, increment/reload destination, HBlank repeat, IRQ.
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for cycle in [
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u64::from(HBLANK_START),
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u64::from(HBLANK_START + CYCLES_PER_LINE),
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] {
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advance_to(&mut machine, cycle);
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for channel in [0, 3] {
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units(&mut machine, channel, 1);
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assert_eq!(machine.last_timing().data_cycles, 2);
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assert_eq!(machine.last_timing().internal_cycles, 2);
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assert!(enabled(&machine, channel));
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}
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assert_eq!(machine.memory().read16(DEST + 8).unwrap(), OTHER as u16);
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assert_eq!(machine.memory().read16(DEST + 32).unwrap(), DATA as u16);
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assert_eq!(machine.memory().read16(IF).unwrap() & 0x900, 0x900);
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}
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assert_eq!(
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u64::from(machine.memory().read16(TIMER_BASE).unwrap()),
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machine.cycles() - start
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);
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}
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