refactor(cpu): share instruction fetch samples with bus history
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18 changed files with 538 additions and 117 deletions
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@ -178,8 +178,7 @@ impl Machine {
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return Ok(StepKind::HaltIdle);
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}
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let (kind, timing) = if self.cpu.take_interrupt(self.memory.irq_pending(), false) {
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self.memory.invalidate_cpu_bus_history();
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self.cpu.refill_pipeline(&self.memory);
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self.cpu.refill_pipeline(&mut self.memory);
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(StepKind::IrqEntry, self.cpu.exception_timing(&self.memory))
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} else {
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(
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