feat(memory): retain aligned Thumb BIOS prefetch words
Snapshot the full word at (executing PC+4)&~3 for Thumb BIOS execution, using strict image reads and incoming instruction state. Keep ARM PC+8 open bus separate and unchanged. Commit snapshots only after successful steps; preserve diagnostic behavior for unavailable lookahead. Add original regression coverage for both code alignments, load widths and lanes, signed and unaligned values, processor modes, sequential fetches, ARM/Thumb transitions, SWI, RAM-backed POP exits, BIOS boundaries, failure retention, and nominal device progression. Record source evidence and explicit pipeline/hardware-validation limits. Darwin arm64 validation: 878 workspace tests and 809 core/demo tests in each of debug and release; 39 Python tests; native ROM window tests in both profiles; ten window/graphics smoke modes; fmt, clippy, and rustdoc. Public ARM, Thumb, memory, and BIOS reports match prior passing reports and match between profiles. No physical-hardware validation claimed.
This commit is contained in:
0xrsydn
parent
efdc288db6
commit
cb4670c245
12 changed files with 427 additions and 25 deletions
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@ -7,6 +7,9 @@ use crate::{
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timing::StepTiming,
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};
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#[path = "thumb_bios_access_tests.rs"]
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mod thumb;
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const ENTRY: u32 = 0x100;
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const DATA: u32 = 0xf233_80a5;
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const OTHER: u32 = 0x1234_5678;
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@ -222,8 +225,8 @@ fn diagnostic_steps_keep_previous_bios_history_but_skipped_instructions_refresh_
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}
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#[test]
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fn thumb_bios_execution_and_missing_lookahead_invalidate_unsupported_history() {
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for (pc, thumb) in [(0x200, true), (0x3ff8, false), (0x3ffc, false)] {
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fn missing_arm_or_thumb_lookahead_invalidates_unsupported_history() {
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for (pc, thumb) in [(0x3ffc, true), (0x3ff8, false), (0x3ffc, false)] {
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let mut bios = image();
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word(&mut bios, pc, if thumb { 0x4720 } else { BX_R4 }); // Thumb BX r4 or ARM BX r4
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let mut memory = bus(LDR, bios);
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287
crates/gba-core/src/cpu/thumb_bios_access_tests.rs
Normal file
287
crates/gba-core/src/cpu/thumb_bios_access_tests.rs
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@ -0,0 +1,287 @@
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//! Thumb BIOS fetches drive a complete aligned word, unlike 16-bit ROM open bus.
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use super::*;
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const THUMB_ENTRY: u32 = 0x300;
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const BX_R5: u16 = 0x4728;
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fn half(bytes: &mut [u8], address: u32, value: u16) {
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bytes[address as usize..address as usize + 2].copy_from_slice(&value.to_le_bytes());
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}
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fn thumb_image(pc: u32, instruction: u16) -> Vec<u8> {
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let mut bios = image();
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half(&mut bios, pc, instruction);
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if pc < 0x3ffc {
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word(&mut bios, (pc + 4) & !3, OTHER);
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}
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bios
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}
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fn enter_thumb(memory: &mut Memory, pc: u32, target_thumb: bool) -> Cpu {
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let mut cpu = Cpu::new(ENTRY);
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cpu.registers[4] = pc | 1;
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cpu.registers[5] = ROM_START | u32::from(target_thumb);
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cpu.step(memory).unwrap(); // Real ARM BX into Thumb BIOS, seed ARM history.
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assert_eq!(cpu.pc(), pc);
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assert_eq!(cpu.instruction_set(), InstructionSet::Thumb);
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cpu
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}
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// Inspect via an independent CPU load without changing the BIOS CPU's state.
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fn protected_word(memory: &mut Memory) -> u32 {
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memory.write32(0x0200_0000, LDR).unwrap();
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let mut probe = Cpu::new(0x0200_0000);
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probe.step(memory).unwrap();
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probe.registers[1]
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}
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#[test]
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fn thumb_exit_retains_both_word_lanes_for_each_code_alignment_and_load_width() {
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for offset in [0, 2] {
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let pc = THUMB_ENTRY + offset;
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for (arm, thumb, expected) in [
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(
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LDR,
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0x6801,
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[0xf233_80a5, 0xa5f2_3380, 0x80a5_f233, 0x3380_a5f2],
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),
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(0xe5d0_1000, 0x7801, [0xa5, 0x80, 0x33, 0xf2]),
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(
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0xe1d0_10b0,
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0x8801,
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[0x80a5, 0xa500_0080, 0xf233, 0x3300_00f2],
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),
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(
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0xe1d0_10d0,
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0x5681,
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[0xffff_ffa5, 0xffff_ff80, 0x33, 0xffff_fff2],
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),
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(
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0xe1d0_10f0,
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0x5e81,
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[0xffff_80a5, 0xffff_ff80, 0xffff_f233, 0xffff_fff2],
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),
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] {
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for target_thumb in [false, true] {
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for address in [0, 0x100, 0x3ffc] {
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for (lane, value) in expected.into_iter().enumerate() {
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let mut bios = thumb_image(pc, BX_R5);
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word(&mut bios, ENTRY + 8, OTHER); // Distinct incoming ARM history.
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word(&mut bios, THUMB_ENTRY + 4, DATA);
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// Poison PC+8, and PC+6's next word for the unaligned case.
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word(&mut bios, THUMB_ENTRY + 8, 0xdead_beef);
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let mut memory = bus(if target_thumb { thumb } else { arm }, bios);
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let mut cpu = enter_thumb(&mut memory, pc, target_thumb);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.pc(), ROM_START);
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cpu.registers[0] = address + lane as u32;
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cpu.flags.carry = true;
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let mut after = cpu.clone();
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after.registers[1] = value;
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after.registers[15] += if target_thumb { 2 } else { 4 };
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let timing = cpu.step_timed(&mut memory).unwrap();
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assert_eq!(cpu, after, "pc={pc:#x} lane={lane} thumb={target_thumb}");
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assert_eq!(timing.data_cycles, 1);
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assert_eq!(timing.internal_cycles, 1);
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assert_eq!(memory.cycles(), 0);
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}
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}
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}
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}
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}
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}
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#[test]
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fn sequential_thumb_steps_sample_the_aligned_fetch_word_without_extra_cycles() {
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let mut bios = thumb_image(THUMB_ENTRY, 0x46c0); // MOV r8,r8
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half(&mut bios, THUMB_ENTRY + 2, 0x46c0);
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half(&mut bios, THUMB_ENTRY + 4, BX_R5);
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// At PC+4 and PC+6: the exit instruction plus a distinct high halfword.
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let first = (OTHER & 0xffff_0000) | u32::from(BX_R5);
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word(&mut bios, THUMB_ENTRY + 8, DATA);
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let mut memory = bus(LDR, bios);
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let mut cpu = enter_thumb(&mut memory, THUMB_ENTRY, false);
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assert_eq!(protected_word(&mut memory), DATA); // Incoming ARM prefetch.
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for expected in [first, first, DATA] {
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let timing = cpu.step_timed(&mut memory).unwrap();
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assert_eq!(timing.data_cycles, 0);
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assert_eq!(protected_word(&mut memory), expected);
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assert_eq!(memory.cycles(), 0);
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}
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assert_eq!(cpu.pc(), ROM_START);
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}
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#[test]
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fn thumb_to_arm_bios_transition_uses_incoming_state_then_refreshes_arm_history() {
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for offset in [0, 2] {
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let mut bios = thumb_image(THUMB_ENTRY + offset, BX_R5);
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word(&mut bios, 0x208, DATA);
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let mut memory = bus(LDR, bios);
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let mut cpu = enter_thumb(&mut memory, THUMB_ENTRY + offset, false);
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cpu.registers[5] = 0x200; // Existing ARM BX r4, now with DATA at PC+8.
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cpu.registers[4] = ROM_START;
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.instruction_set(), InstructionSet::Arm);
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assert_eq!(protected_word(&mut memory), OTHER);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.pc(), ROM_START);
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assert_eq!(protected_word(&mut memory), DATA);
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}
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}
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#[test]
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fn thumb_bios_protection_remains_pc_based_in_every_processor_mode() {
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for mode in [
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Mode::User,
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Mode::System,
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Mode::Fiq,
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Mode::Irq,
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Mode::Supervisor,
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Mode::Abort,
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Mode::Undefined,
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] {
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for offset in [0, 2] {
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let pc = THUMB_ENTRY + offset;
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let mut bios = thumb_image(pc, 0x6801); // LDR r1,[r0] inside BIOS.
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half(&mut bios, pc + 2, BX_R5);
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let mut memory = bus(LDR, bios);
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let mut cpu = enter_thumb(&mut memory, pc, false);
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cpu.apply_status(0xb000_00e0 | mode as u32, mode);
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cpu.registers[0] = ENTRY + 8;
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], DATA); // Raw BIOS data, not retained OTHER.
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assert_eq!(cpu.cpsr(), 0xb000_00e0 | mode as u32);
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cpu.step(&mut memory).unwrap(); // BX to ARM ROM.
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let expected = memory.read32((pc + 6) & !3).unwrap();
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cpu.registers[0] = ENTRY + 8;
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], expected);
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assert_eq!(cpu.cpsr(), 0xb000_00c0 | mode as u32);
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}
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}
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}
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#[test]
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fn thumb_pop_pc_retains_prefetch_not_stack_data_and_stays_thumb() {
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for offset in [0, 2] {
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let mut memory = bus(0x6801, thumb_image(THUMB_ENTRY + offset, 0xbd00)); // POP {pc}
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let mut cpu = enter_thumb(&mut memory, THUMB_ENTRY + offset, true);
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cpu.registers[13] = 0x0300_0100;
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memory.write32(0x0300_0100, ROM_START).unwrap();
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let timing = cpu.step_timed(&mut memory).unwrap();
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assert_eq!(timing.data_cycles, 1);
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assert_eq!(cpu.registers[13], 0x0300_0104);
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assert_eq!(cpu.instruction_set(), InstructionSet::Thumb);
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assert_eq!(cpu.pc(), ROM_START);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], OTHER);
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}
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}
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#[test]
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fn thumb_swi_enters_arm_and_the_next_bios_instruction_replaces_thumb_history() {
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for offset in [0, 2] {
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let mut bios = thumb_image(THUMB_ENTRY + offset, 0xdf00); // SWI #0
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word(&mut bios, 8, 0xe12f_ff15); // BX r5
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word(&mut bios, 16, DATA);
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let mut memory = bus(LDR, bios);
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let mut cpu = enter_thumb(&mut memory, THUMB_ENTRY + offset, false);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.pc(), 8);
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assert_eq!(cpu.mode(), Mode::Supervisor);
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assert_eq!(cpu.instruction_set(), InstructionSet::Arm);
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assert_eq!(protected_word(&mut memory), OTHER);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.pc(), ROM_START);
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], DATA);
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}
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}
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#[test]
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fn last_complete_thumb_fetch_word_is_valid_at_both_alignments() {
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for pc in [0x3ff8, 0x3ffa] {
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let mut memory = bus(LDR, thumb_image(pc, BX_R5));
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let mut cpu = enter_thumb(&mut memory, pc, false);
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cpu.step(&mut memory).unwrap();
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], OTHER);
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}
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for pc in [0x3ffc, 0x3ffe] {
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let mut memory = bus(LDR, thumb_image(pc, BX_R5));
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let mut cpu = enter_thumb(&mut memory, pc, false);
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cpu.step(&mut memory).unwrap(); // Missing lookahead does not fail BX itself.
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assert_eq!(cpu.pc(), ROM_START);
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut memory),
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Err(CpuError::Memory(MemoryError::Unmapped(0)))
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);
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assert_eq!(cpu, before);
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}
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}
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#[test]
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fn failed_thumb_steps_keep_previous_history_and_clear_access_context() {
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for instruction in [0xde00, 0x6801] {
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// Undefined instruction / failing LDR.
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let mut memory = bus(LDR, thumb_image(THUMB_ENTRY, instruction));
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let mut cpu = enter_thumb(&mut memory, THUMB_ENTRY, false);
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cpu.registers[0] = 0x0e00_0000;
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let before = cpu.clone();
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assert!(cpu.step_timed(&mut memory).is_err());
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assert_eq!(cpu, before);
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assert_eq!(memory.cycles(), 0);
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assert_eq!(memory.read32(THUMB_ENTRY + 4).unwrap(), OTHER); // Raw host read.
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assert_eq!(protected_word(&mut memory), DATA); // Previous ARM history retained.
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}
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}
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#[test]
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fn outside_thumb_execution_keeps_history_but_does_not_enable_general_open_bus() {
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let mut memory = bus(0x6801, thumb_image(THUMB_ENTRY, BX_R5));
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let mut cpu = enter_thumb(&mut memory, THUMB_ENTRY, true);
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cpu.step(&mut memory).unwrap();
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assert_eq!(protected_word(&mut memory), OTHER);
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cpu.registers[0] = 0x4000;
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut memory),
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Err(CpuError::Memory(MemoryError::Unmapped(0x4000)))
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);
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assert_eq!(cpu, before);
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assert_eq!(memory.read32(0x4000), Err(MemoryError::Unmapped(0x4000)));
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assert_eq!(protected_word(&mut memory), OTHER);
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cpu.registers[0] = 0;
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cpu.step(&mut memory).unwrap();
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assert_eq!(cpu.registers[1], OTHER);
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}
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#[test]
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fn machine_steps_charge_thumb_exit_and_protected_load_without_snapshot_accesses() {
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for offset in [0, 2] {
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let mut memory = bus(LDR, thumb_image(THUMB_ENTRY + offset, BX_R5));
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let cpu = enter_thumb(&mut memory, THUMB_ENTRY + offset, false);
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memory.write32(TIMER_BASE, 0x0080_0000).unwrap();
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let mut machine = Machine::new(cpu, memory);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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let cycles = machine.cycles();
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assert_eq!(machine.last_timing().data_cycles, 0);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[1], OTHER);
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assert_eq!(
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machine.last_timing(),
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StepTiming {
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code_cycles: 8,
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data_cycles: 1,
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internal_cycles: 1,
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idle_cycles: 0,
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}
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);
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assert_eq!(machine.cycles(), cycles + 10);
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assert_eq!(
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u64::from(machine.memory().read16(TIMER_BASE).unwrap()),
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machine.cycles()
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);
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}
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}
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@ -57,12 +57,13 @@ fn vram_index(address: u32) -> usize {
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struct CpuAccess {
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pc: u32,
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arm_prefetch: Option<u32>,
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bios_prefetch: Option<u32>,
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}
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/// Work/video/palette RAM, OAM, cartridge ROM, optional BIOS, and supported I/O.
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/// ARM data reads from unused memory return a PC+8 snapshot when available.
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/// CPU data reads of BIOS from outside BIOS use its retained ARM PC+8 snapshot.
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/// Thumb BIOS prefetch, general Thumb open bus, and DMA bus latches are not modeled.
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/// Protected BIOS reads retain an ARM PC+8 or aligned Thumb PC+4 word snapshot.
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/// General Thumb open bus, a full fetch pipeline, and DMA bus latches are not modeled.
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pub struct Memory {
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external_ram: Vec<u8>,
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internal_ram: Vec<u8>,
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@ -333,17 +334,31 @@ impl Memory {
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// Sample before execution, without data timing or open-bus recursion.
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// Missing lookahead bytes must not fail an instruction that never uses them.
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let arm_prefetch = match instruction_set {
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InstructionSet::Arm => self.snapshot_arm_prefetch(pc),
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InstructionSet::Arm => self.snapshot_mapped_word(pc.wrapping_add(8)),
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InstructionSet::Thumb => None,
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};
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self.cpu_access = Some(CpuAccess { pc, arm_prefetch });
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let bios_prefetch = if pc < BIOS_SIZE as u32 {
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match instruction_set {
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InstructionSet::Arm => arm_prefetch,
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// BIOS drives a full 32-bit word for a Thumb halfword fetch.
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// Preserve both lanes of the aligned PC+4 word, not a repeated halfword.
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InstructionSet::Thumb => self.snapshot_mapped_word((pc + 4) & !3),
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}
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} else {
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None
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};
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self.cpu_access = Some(CpuAccess {
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pc,
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arm_prefetch,
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bios_prefetch,
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});
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}
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fn snapshot_arm_prefetch(&self, pc: u32) -> Option<u32> {
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fn snapshot_mapped_word(&self, address: u32) -> Option<u32> {
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let mut bytes = [0; 4];
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for (offset, byte) in bytes.iter_mut().enumerate() {
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*byte = self
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.read_mapped_byte(pc.wrapping_add(8 + offset as u32))
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.read_mapped_byte(address.wrapping_add(offset as u32))
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.ok()?;
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}
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Some(u32::from_le_bytes(bytes))
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@ -353,8 +368,8 @@ impl Memory {
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if let Some(access) = self.cpu_access.take() {
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if succeeded && access.pc < BIOS_SIZE as u32 {
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// Commit only successful instruction snapshots under our diagnostic policy.
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// Thumb BIOS execution or missing lookahead invalidates the known value.
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self.bios_prefetch = access.arm_prefetch;
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// Missing lookahead invalidates history rather than exposing stale bytes.
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self.bios_prefetch = access.bios_prefetch;
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}
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}
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}
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