fix(timers): apply machine accesses at bus completion
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0xrsydn
parent
8930ea93b4
commit
bfecc87e84
20 changed files with 765 additions and 137 deletions
346
crates/gba-core/src/memory/timer_step_tests.rs
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346
crates/gba-core/src/memory/timer_step_tests.rs
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@ -0,0 +1,346 @@
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//! Original checks of timer transaction ownership and bus-completion sampling.
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use super::{timing_event_tests::prepared, *};
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use crate::{
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cpu::Cpu,
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display::HBLANK_START,
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dma::DMA_STRIDE,
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io::{DISPSTAT, HALTCNT, IE, IF, IME, TIMER_BASE, WAITCNT},
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machine::{Machine, StepKind},
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};
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const NOP: u32 = 0xe1a0_0000;
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const RAM: u32 = 0x0300_1000;
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fn start(memory: &mut Memory, index: u32, reload: u16, control: u16) {
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memory
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.write32(
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TIMER_BASE + index * 4,
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u32::from(reload) | u32::from(control) << 16,
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)
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.unwrap();
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}
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fn dma(memory: &mut Memory, source: u32, destination: u32, count: u16) {
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let base = DMA_BASE + 3 * DMA_STRIDE;
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memory.write32(base, source).unwrap();
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memory.write32(base + 4, destination).unwrap();
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memory
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.write32(base + 8, 0x8400_0000 | u32::from(count))
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.unwrap();
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}
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#[test]
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fn arm_and_thumb_timer_loads_observe_source_and_data_but_not_trailing_internal_cycles() {
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for (thumb, instruction, sample, final_count) in
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[(false, 0xe591_0000, 7, 8), (true, 0x6808, 4, 5)]
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{
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let (cpu, mut memory) = prepared(thumb, &[instruction], &[(1, TIMER_BASE)]);
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start(&mut memory, 0, 0, 0x80);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[0], 0x0080_0000 | sample);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), final_count);
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assert_eq!(machine.cycles(), u64::from(final_count));
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assert!(machine.memory().timer_step.get().is_none());
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}
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}
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#[test]
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fn byte_halfword_and_word_lanes_share_one_completed_access() {
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for (instruction, address, expected) in [
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(0xe5d1_0000, TIMER_BASE, 6),
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(0xe5d1_0000, TIMER_BASE + 1, 1),
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(0xe1d1_00b0, TIMER_BASE, 0x106),
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(0xe591_0000, TIMER_BASE, 0x0080_0106),
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] {
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let (cpu, mut memory) = prepared(false, &[instruction], &[(1, address)]);
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start(&mut memory, 0, 0xff, 0x80);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[0], expected);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0x107);
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assert_eq!(machine.cycles(), 8);
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}
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}
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#[test]
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fn starting_and_stopping_timers_take_effect_after_the_store_bus_cycle() {
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for running in [false, true] {
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let control = if running { 0 } else { 0x0080_0000 };
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let (cpu, mut memory) =
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prepared(false, &[0xe581_0000, NOP], &[(0, control), (1, TIMER_BASE)]);
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if running {
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start(&mut memory, 0, 0, 0x80);
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}
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cycles(), 7);
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assert_eq!(
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machine.memory().read16(TIMER_BASE).unwrap(),
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if running { 7 } else { 0 }
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);
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machine.step().unwrap(); // Store left N: this ROM fetch costs eight cycles.
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assert_eq!(
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machine.memory().read16(TIMER_BASE).unwrap(),
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if running { 7 } else { 8 }
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);
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assert_eq!(machine.cycles(), 15);
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}
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}
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#[test]
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fn block_timer_accesses_keep_distinct_word_phases() {
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let (cpu, mut memory) = prepared(false, &[0xe891_0005], &[(1, TIMER_BASE)]); // LDM r1,{r0,r2}
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start(&mut memory, 0, 0, 0x80);
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start(&mut memory, 1, 0, 0x80);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[0], 0x0080_0007);
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assert_eq!(machine.cpu().registers()[2], 0x0080_0008);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 9);
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assert_eq!(machine.memory().read16(TIMER_BASE + 4).unwrap(), 9);
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let (cpu, memory) = prepared(
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false,
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&[0xe880_0006],
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&[(0, TIMER_BASE), (1, 0x0080_0000), (2, 0x0080_0000)],
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);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 1);
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assert_eq!(machine.memory().read16(TIMER_BASE + 4).unwrap(), 0);
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assert_eq!(machine.cycles(), 8);
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}
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#[test]
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fn reload_changes_preserve_pre_write_overflows_and_prescaler_phase() {
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// Overflow during source fetch uses the old reload, not the value stored afterward.
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let (cpu, mut memory) = prepared(false, &[0xe1c1_00b0], &[(0, 0x1234), (1, TIMER_BASE)]);
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start(&mut memory, 0, 0xfffa, 0xc0);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xfffb);
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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machine.memory_mut().advance_cycles(5);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0x1234);
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// A read crossing a prescaler edge must retain the remainder for the next step.
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let (cpu, mut memory) = prepared(false, &[0xe591_0000], &[(1, TIMER_BASE)]);
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start(&mut memory, 0, 0, 0x81);
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memory.advance_cycles(60);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[0], 0x0081_0001);
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machine.memory_mut().advance_cycles(59);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 1);
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machine.memory_mut().advance_cycles(1);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 2);
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}
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#[test]
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fn cascades_and_timer_irq_bits_are_visible_at_the_read_phase() {
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let (cpu, mut memory) = prepared(false, &[0xe591_0000], &[(1, TIMER_BASE + 4)]);
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start(&mut memory, 0, 0xfffe, 0xc0);
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start(&mut memory, 1, 0xfffe, 0xc4);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap(); // Source+data=7 gives three timer0 pulses and one timer1 overflow.
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assert_eq!(machine.cpu().registers()[0], 0x00c4_ffff);
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assert_eq!(machine.memory().read16(TIMER_BASE + 4).unwrap(), 0xfffe);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0x18);
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let (cpu, mut memory) = prepared(false, &[0xe591_0000], &[(1, IE)]);
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start(&mut memory, 0, 0xfffa, 0xc0);
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memory.write16(IE, 8).unwrap();
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memory.write16(IME, 1).unwrap();
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let mut machine = Machine::new(cpu, memory);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[0], 0x0008_0008); // Word IE+IF, coherent timer flag.
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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}
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#[test]
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fn if_acknowledgement_clears_earlier_timer_events_but_not_later_ones() {
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for (instruction, reload, expected) in [(0xe1c1_00b0, 0xfffa, 0), (0xe141_0092, 0xffff, 8)] {
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let (cpu, mut memory) = prepared(false, &[instruction], &[(0, 8), (1, IF), (2, 8)]);
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start(&mut memory, 0, reload, 0xc0);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.memory().read16(IF).unwrap(), expected);
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if instruction == 0xe141_0092 {
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// SWPB acknowledges at the second data access; its final I cycle raises IF again.
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assert_eq!(machine.cpu().registers()[0], 8);
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}
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}
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}
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#[test]
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fn failed_instructions_discard_partial_timer_progress_and_pending_irqs() {
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for (instruction, base) in [
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(0xe591_0000, 0x0e00_0000),
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(0xe891_0005, TIMER_BASE + 12),
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(0xe881_0005, TIMER_BASE + 12),
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(0xffff_ffff, 0),
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] {
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let (cpu, mut memory) = prepared(false, &[instruction], &[(1, base)]);
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start(&mut memory, 0, 0xfffc, 0xc0);
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let before = memory.io.timer_step();
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let cpu_before = cpu.clone();
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let mut machine = Machine::new(cpu, memory);
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for _ in 0..2 {
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assert!(machine.step().is_err());
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assert_eq!(machine.memory().io.timer_step(), before);
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assert_eq!(machine.cpu(), &cpu_before);
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assert_eq!(machine.cycles(), 0);
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assert!(machine.memory().timer_step.get().is_none());
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assert!(machine.memory().cpu_timing.get().is_none());
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}
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}
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// A missing current instruction fails before CpuTiming starts, but must still discard TimerStep.
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let mut memory = Memory::new(Vec::new()).unwrap();
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start(&mut memory, 0, 0xffff, 0xc0);
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let mut machine = Machine::new(Cpu::new(ROM_START), memory);
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assert!(machine.step().is_err());
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assert!(machine.memory().timer_step.get().is_none());
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 0xffff);
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}
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#[test]
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fn cpu_only_apis_and_host_reads_do_not_advance_timer_devices() {
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for prefetch in [0, 0x4000] {
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for timed in [false, true] {
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let (mut cpu, mut memory) = prepared(false, &[0xe591_0000], &[(1, TIMER_BASE)]);
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memory.write16(WAITCNT, prefetch).unwrap();
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start(&mut memory, 0, 123, 0x80);
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let before = memory.io.timer_step();
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if timed {
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cpu.step_timed(&mut memory).unwrap();
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} else {
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cpu.step(&mut memory).unwrap();
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}
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assert_eq!(cpu.registers()[0], 0x0080_007b);
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 123);
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assert_eq!(memory.io.timer_step(), before);
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assert_eq!(memory.cycles(), 0);
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}
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}
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}
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#[test]
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fn dma_samples_timers_after_startup_and_source_and_writes_after_destination() {
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let mut memory = Memory::new(Vec::new()).unwrap();
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start(&mut memory, 0, 0, 0x80);
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dma(&mut memory, TIMER_BASE, RAM, 1);
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memory.step_dma().unwrap().unwrap();
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assert_eq!(memory.read32(RAM).unwrap(), 0x0080_0003);
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 4);
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assert_eq!(memory.cycles(), 4);
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let mut memory = Memory::new(Vec::new()).unwrap();
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memory.write32(RAM, 0x0080_0000).unwrap();
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memory.write32(RAM + 4, 0x0080_0000).unwrap();
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dma(&mut memory, RAM, TIMER_BASE, 2);
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memory.step_dma().unwrap().unwrap();
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 0);
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memory.step_dma().unwrap().unwrap();
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assert_eq!(memory.read16(TIMER_BASE).unwrap(), 2);
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assert_eq!(memory.read16(TIMER_BASE + 4).unwrap(), 0);
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assert_eq!(memory.cycles(), 6);
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}
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#[test]
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fn dma_failures_preserve_timers_and_if_and_clear_the_transaction() {
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for (source, destination) in [(0x0e00_0000, RAM), (TIMER_BASE, ROM_START)] {
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let mut memory = Memory::new(Vec::new()).unwrap();
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start(&mut memory, 0, 0xffff, 0xc0);
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let before = memory.io.timer_step();
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dma(&mut memory, source, destination, 1);
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assert!(memory.step_dma().is_err());
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assert_eq!(memory.io.timer_step(), before);
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assert!(memory.timer_step.get().is_none());
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assert_eq!(memory.cycles(), 0);
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}
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}
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#[test]
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fn display_capture_splits_do_not_advance_committed_timers_twice() {
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for capture in [false, true] {
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let (cpu, mut memory) = prepared(false, &[0xe891_007d], &[(1, 0x0200_1000)]);
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memory.set_scanline_rendering(capture);
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memory.advance_cycles(HBLANK_START - 2);
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start(&mut memory, 0, 0, 0x80);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap(); // Source 6, six EWRAM words 36, internal 1.
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assert_eq!(machine.last_timing().total(), 43);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 43);
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assert_eq!(machine.cycles(), u64::from(HBLANK_START - 2 + 43));
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}
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}
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#[test]
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fn timer_flag_commit_preserves_other_irq_sources() {
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for (instruction, expected) in [(0xe1d1_00b0, 0xa), (0xe1c1_00b0, 2)] {
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let (cpu, mut memory) = prepared(false, &[instruction], &[(0, 8), (1, IF)]);
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memory.write16(DISPSTAT, 0x10).unwrap();
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memory.advance_cycles(HBLANK_START);
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assert_eq!(memory.read16(IF).unwrap(), 2);
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start(&mut memory, 0, 0xfffa, 0xc0);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.memory().read16(IF).unwrap(), expected);
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if instruction == 0xe1d1_00b0 {
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assert_eq!(machine.cpu().registers()[0], 0xa);
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}
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}
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}
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#[test]
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fn bios_power_store_pays_its_cycles_and_new_timer_irq_wakes_only_halt() {
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for stop in [false, true] {
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let (mut cpu, mut memory) = prepared(
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false,
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&[0xe12f_ff1c],
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&[(0, if stop { 0x80 } else { 0 }), (1, HALTCNT), (12, 0x100)],
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);
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memory.bios.as_mut().unwrap()[0x100..0x104].copy_from_slice(&0xe5c1_0000_u32.to_le_bytes());
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cpu.step(&mut memory).unwrap(); // BX into original BIOS STRB r0,[r1].
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start(&mut memory, 0, 0xffff, 0xc0);
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memory.write16(IE, 8).unwrap();
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cycles(), 2);
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assert_eq!(machine.memory().read16(IF).unwrap(), 8);
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assert!(!machine.halted());
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assert_eq!(machine.stopped(), stop);
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if stop {
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let before = machine.memory().io.timer_step();
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assert_eq!(machine.step().unwrap(), StepKind::StopIdle);
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assert_eq!(machine.memory().io.timer_step(), before);
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assert_eq!(machine.cycles(), 2);
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} else {
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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}
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}
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}
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#[test]
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fn halt_and_stop_keep_their_clock_ownership() {
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for stop in [false, true] {
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let mut memory = Memory::new(Vec::new()).unwrap();
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start(&mut memory, 0, 0, 0x80);
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memory.write8(HALTCNT, if stop { 0x80 } else { 0 }).unwrap();
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let mut machine = Machine::new(Cpu::new(ROM_START), memory);
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assert_eq!(
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machine.step().unwrap(),
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if stop {
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StepKind::StopIdle
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} else {
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StepKind::HaltIdle
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}
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);
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assert_eq!(
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u64::from(machine.memory().read16(TIMER_BASE).unwrap()),
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machine.cycles()
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);
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assert!(machine.memory().timer_step.get().is_none());
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}
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}
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