feat(audio): implement PSG pulse channel 2
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0xrsydn
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aee3621513
15 changed files with 457 additions and 89 deletions
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@ -1,4 +1,4 @@
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//! Nominal Direct Sound and PSG pulse channel 1. No host audio output.
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//! Nominal Direct Sound and PSG pulse channels 1–2. No host audio output.
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mod pulse;
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use pulse::Pulse;
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@ -78,7 +78,7 @@ impl Fifo {
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pub(crate) struct Audio {
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enabled: bool,
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psg: [u16; 17],
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pulse: Pulse,
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pulses: [Pulse; 2],
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sequencer_phase: u16,
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next_step: u8,
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control: u16,
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@ -99,10 +99,7 @@ impl Audio {
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{
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return Some("reserved PSG volume selection");
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}
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if self.enabled
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&& matches!(address, 0x0400_006d | 0x0400_0075 | 0x0400_007d)
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&& value & 0x80 != 0
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{
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if self.enabled && matches!(address, 0x0400_0075 | 0x0400_007d) && value & 0x80 != 0 {
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Some("PSG channel trigger (synthesis not implemented)")
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} else {
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None
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@ -113,9 +110,20 @@ impl Audio {
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1 ^ usize::from((self.psg[8] >> 6) & 1)
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}
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/// Channel 2 has no sweep register. Its register gap must not alias any
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/// pulse state, particularly the shared engine's sweep configuration.
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fn pulse_register(address: u32) -> Option<(usize, u32)> {
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match address {
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SOUND_START..=0x0400_0065 => Some((0, address - SOUND_START)),
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0x0400_0068..=0x0400_0069 => Some((1, address - 0x0400_0066)),
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0x0400_006c..=0x0400_006d => Some((1, address - 0x0400_0068)),
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_ => None,
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}
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}
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pub(crate) fn read8(&self, address: u32) -> Option<u8> {
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if (SOUND_START..=SOUND_START + 5).contains(&address) {
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return Some(self.pulse.read(address - SOUND_START));
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if let Some((index, offset)) = Self::pulse_register(address) {
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return Some(self.pulses[index].read(offset));
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}
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if (WAVE_RAM..FIFO_A).contains(&address) {
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return Some(self.wave[self.wave_bank()][(address - WAVE_RAM) as usize]);
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@ -123,9 +131,7 @@ impl Audio {
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let value = match address & !1 {
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SOUND_START..=0x0400_0080 => {
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let mask = match address & !1 {
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0x0400_0060 => 0x007f,
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0x0400_0062 | 0x0400_0068 => 0xffc0,
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0x0400_0064 | 0x0400_006c | 0x0400_0074 => 0x4000,
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0x0400_0074 => 0x4000,
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0x0400_0070 => 0x00e0,
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0x0400_0072 => 0xe000,
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0x0400_0078 => 0xff00,
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@ -136,7 +142,11 @@ impl Audio {
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self.psg[((address - SOUND_START) / 2) as usize] & mask
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}
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SOUNDCNT_H => self.control,
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SOUNDCNT_X => (u16::from(self.enabled) << 7) | u16::from(self.pulse.active),
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SOUNDCNT_X => {
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(u16::from(self.enabled) << 7)
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| u16::from(self.pulses[0].active)
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| (u16::from(self.pulses[1].active) << 1)
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}
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SOUNDBIAS => self.bias,
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0x0400_0086 | 0x0400_008a => 0,
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_ => return None, // FIFO is write-only; open-bus readback is not modeled.
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@ -156,9 +166,10 @@ impl Audio {
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self.wave[self.wave_bank()][(address - WAVE_RAM) as usize] = value;
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continue;
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}
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if self.enabled && (SOUND_START..=SOUND_START + 5).contains(&address) {
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self.pulse
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.write(address - SOUND_START, value, self.next_step);
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if let Some((index, offset)) = Self::pulse_register(address) {
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if self.enabled {
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self.pulses[index].write(offset, value, self.next_step);
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}
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continue;
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}
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let shift = (address & 1) * 8;
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@ -181,7 +192,7 @@ impl Audio {
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SOUNDCNT_X if address & 1 == 0 => {
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if self.enabled && value & 0x80 == 0 {
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self.psg = [0; 17];
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self.pulse = Pulse::default();
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self.pulses = [Pulse::default(); 2];
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for fifo in &mut self.fifo {
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fifo.reset_queue();
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}
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@ -207,11 +218,15 @@ impl Audio {
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}
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while cycles != 0 {
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let count = cycles.min(SEQUENCER_PERIOD - u32::from(self.sequencer_phase));
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self.pulse.advance(count);
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for pulse in &mut self.pulses {
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pulse.advance(count);
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}
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let phase = u32::from(self.sequencer_phase) + count;
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if phase == SEQUENCER_PERIOD {
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self.sequencer_phase = 0;
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self.pulse.clock(self.next_step);
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for pulse in &mut self.pulses {
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pulse.clock(self.next_step);
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}
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self.next_step = (self.next_step + 1) & 7;
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} else {
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self.sequencer_phase = phase as u16;
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@ -256,10 +271,15 @@ impl Audio {
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let psg_control = self.psg[16];
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let ratio = [1, 2, 4, 0][usize::from(self.control & 3)];
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for (side, level) in sides.iter_mut().enumerate() {
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if psg_control & (1 << (8 + side * 4)) != 0 {
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let volume = ((psg_control >> (side * 4)) & 7) as i16 + 1;
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*level += (self.pulse.sample() * volume * ratio) >> 2;
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let mut psg_sample = 0;
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for (index, pulse) in self.pulses.iter().enumerate() {
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if psg_control & (1 << (8 + side * 4 + index)) != 0 {
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psg_sample += pulse.sample();
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}
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}
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let volume = ((psg_control >> (side * 4)) & 7) as i16 + 1;
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// Sum PSG channels before scaling, so fractional bits are discarded once.
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*level += (psg_sample * volume * ratio) >> 2;
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*level = (*level + (self.bias & 0x3ff) as i16).clamp(0, 1023) - 512;
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}
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StereoLevel {
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@ -1,4 +1,5 @@
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//! Nominal channel 1 oscillator and modulation units. No host-clock dependency.
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//! Shared nominal pulse oscillator and modulation units. No host-clock dependency.
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//! Channel 2 never receives sweep-register writes, so its sweep remains disabled.
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub(super) struct Pulse {
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@ -10,7 +10,9 @@ fn sound(memory: &mut Memory, period: u16) {
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memory.write16(SOUNDBIAS, 0x200).unwrap();
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memory.write16(SOUNDCNT_H, 0x0304).unwrap();
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memory.write16(0x04000062, 0xf080).unwrap();
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memory.write16(0x04000064, 0x87ff).unwrap(); // Running pulse, unrouted; rollback must include it.
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memory.write16(0x04000064, 0x87ff).unwrap();
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memory.write16(0x04000068, 0xf080).unwrap();
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memory.write16(0x0400006c, 0x87ff).unwrap(); // Both pulses run unrouted; rollback must include them.
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memory
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.write32(
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TIMER_BASE,
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@ -21,26 +23,57 @@ fn sound(memory: &mut Memory, period: u16) {
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#[test]
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fn pulse_status_load_observes_length_expiry_at_bus_completion() {
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let (cpu, mut memory) = prepared(false, &[0xe5910000], &[(1, SOUNDCNT_X)]);
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sound(&mut memory, 1000);
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memory.write16(0x04000062, 0xf03f).unwrap();
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memory.write16(0x04000064, 0xc7ff).unwrap();
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memory.advance_cycles(32768 - 7);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[0], 0x80);
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assert_eq!(machine.memory().read16(SOUNDCNT_X).unwrap(), 0x80);
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for (index, duty, frequency) in [(0, 0x04000062, 0x04000064), (1, 0x04000068, 0x0400006c)] {
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let (cpu, mut memory) = prepared(false, &[0xe5910000], &[(1, SOUNDCNT_X)]);
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sound(&mut memory, 1000);
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memory.write16(duty, 0xf03f).unwrap();
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memory.write16(frequency, 0xc7ff).unwrap();
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memory.advance_cycles(32768 - 7);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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let status = 0x83 ^ (1 << index); // The other channel remains active.
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assert_eq!(machine.cpu().registers()[0], status);
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assert_eq!(machine.memory().read16(SOUNDCNT_X).unwrap(), status as u16);
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}
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}
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#[test]
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fn pulse_trigger_reloads_timer_at_store_completion() {
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let (cpu, mut memory) = prepared(false, &[0xe5810000], &[(0, 0x87ff), (1, 0x04000064)]);
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for (index, frequency) in [0x04000064, 0x0400006c].into_iter().enumerate() {
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let (cpu, mut memory) = prepared(false, &[0xe5810000], &[(0, 0x87ff), (1, frequency)]);
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sound(&mut memory, 1000);
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memory
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.write16(0x04000080, 0x77 | (0x1100 << index))
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.unwrap();
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memory.write16(SOUNDCNT_H, 2).unwrap();
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cycles(), 7);
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machine.memory_mut().advance_cycles(15);
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assert_eq!(machine.memory().audio_level().left, 120);
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machine.memory_mut().advance_cycles(1);
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assert_eq!(machine.memory().audio_level().left, -120);
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}
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}
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#[test]
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fn successful_dma_trigger_starts_channel2_after_destination_bus_cycles() {
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let (cpu, mut memory) = prepared(false, &[0xe1a00000], &[]);
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sound(&mut memory, 1000);
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memory.write16(0x04000080, 0x1177).unwrap();
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memory.write16(0x04000080, 0x2277).unwrap();
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memory.write16(SOUNDCNT_H, 2).unwrap();
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memory.write8(0x04000069, 0).unwrap();
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memory.write8(0x04000069, 0xf0).unwrap(); // DAC gate restored, still needs a trigger.
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memory.write32(0x02000000, 0x87ff).unwrap();
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memory.write32(DMA_BASE, 0x02000000).unwrap();
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memory.write32(DMA_BASE + 4, 0x0400006c).unwrap();
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memory.write32(DMA_BASE + 8, 0x84000001).unwrap();
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.cycles(), 7);
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assert_eq!(
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machine.step().unwrap(),
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crate::machine::StepKind::Dma { channel: 0 }
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);
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assert_eq!(machine.memory().read16(SOUNDCNT_X).unwrap(), 0x83);
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machine.memory_mut().advance_cycles(15);
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assert_eq!(machine.memory().audio_level().left, 120);
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machine.memory_mut().advance_cycles(1);
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@ -95,7 +128,7 @@ fn failed_cpu_load_rolls_back_timer_audio_and_pending_refill_requests() {
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#[test]
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fn failed_dma_source_and_destination_restore_audio_after_speculative_timer_edges() {
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for (source, destination, word) in [(FIFO_A, 0x02001000, 0), (0x02000000, 0x0400006c, 0x8000)] {
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for (source, destination, word) in [(FIFO_A, 0x02001000, 0), (0x02000000, 0x04000074, 0x8000)] {
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let (cpu, mut memory) = prepared(false, &[0xe1a00000], &[]);
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sound(&mut memory, 1);
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memory.write32(FIFO_A, 0x04030201).unwrap();
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@ -113,6 +146,35 @@ fn failed_dma_source_and_destination_restore_audio_after_speculative_timer_edges
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}
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}
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#[test]
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fn arm_block_store_rejects_later_wave_trigger_before_committing_channel2_trigger() {
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let (cpu, mut memory) = prepared(
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false,
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&[0xe8a0001e],
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&[
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(0, 0x04000068),
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(1, 0xf080),
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(2, 0x87ff),
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(3, 0),
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(4, 0x8000),
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],
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); // STMIA r0!,{r1-r4}: channel2 configuration/trigger, wave configuration/trigger.
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memory.write16(SOUNDCNT_X, 0x80).unwrap();
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let audio = memory.io.audio;
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let mut machine = Machine::new(cpu, memory);
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let cpu = machine.cpu().clone();
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for _ in 0..2 {
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assert!(machine
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.step()
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.unwrap_err()
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.to_string()
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.contains("PSG channel trigger"));
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assert_eq!(machine.memory().io.audio, audio);
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assert_eq!(machine.cpu(), &cpu);
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assert_eq!(machine.cycles(), 0);
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}
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}
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#[test]
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fn batch_validation_simulates_sound_enable_and_disable_before_committing_any_write() {
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let mut memory = Memory::new(vec![]).unwrap();
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@ -121,7 +183,9 @@ fn batch_validation_simulates_sound_enable_and_disable_before_committing_any_wri
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.write_words(&[
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(0x02000000, 0x11223344),
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(SOUNDCNT_X, 0x80),
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(0x0400006c, 0x8000),
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(0x04000068, 0xf080),
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(0x0400006c, 0x87ff),
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(0x04000074, 0x8000),
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])
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.is_err());
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assert_eq!(memory.read32(0x02000000).unwrap(), 0);
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