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fix(cpu): support single-load writeback register aliases

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Allow ARM LDR/LDRB/LDRH/LDRSB/LDRSH to share non-PC base and destination registers with writeback. Keep the loaded value after computing addresses from incoming operands. Preserve PC restrictions, unsupported user transfers, store behavior, and atomic memory diagnostics.

Add original regressions for index modes, offsets, widths, alignment, sign extension, all active banks, timing, I/O/IRQ ordering, and failures. The unchanged pinned public ARM ROM progresses past tests 360 and 361, then fails at test 362 on an unmapped 0x80000000 read; no full-suite pass is claimed.

Verified on Darwin arm64: debug/release workspace and core suites, Python adapter tests, Clippy, rustdoc, native ROM-window checks, and all ten demo smoke tests. Document the new behavior and next memory-access blocker.
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0xrsydn 2026-10-05 20:15:18 +07:00
commit ab625dc55d
11 changed files with 367 additions and 12 deletions
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docs/rom-tests.md
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@ -131,7 +131,7 @@ They do not hash ROM contents; record source revisions and file checksums alongs
## Next validation stage
The first public integration is [jsmolka/gba-tests ARM](public-arm-tests.md), with a verified result-register checkpoint and a known failing baseline.
Fix its next unsupported load/writeback alias case before claiming the full ARM ROM passes.
Investigate its next unsupported high-address read at test 362 before claiming the full ARM ROM passes.
For further public ARM7TDMI/GBA tests, inspect their source, license, entry assumptions, and result protocol.
Pin source revisions and build instructions before comparing emulator changes.
Adapt suites to verified completion addresses and result locations; do not guess them or treat timeouts as passes.