feat(memory): support ARM unused-memory open-bus reads
Snapshot mapped PC+8 bytes for ARM data reads in the documented unused ranges. Preserve strict host/fetch/Thumb/DMA diagnostics, missing-ROM errors, existing write rules, and nominal timing. Add original regressions and document the bounded model. The unmodified pinned jsmolka ARM ROM now reaches its verified checkpoint with r12=0 in debug and release: 1344 steps and 11257 nominal cycles. No ROM, manifest, or assertion changes. Validated on Darwin arm64: 842 workspace tests in debug and release; 773 core/demo tests separately; Python adapter tests; native ROM windows; all ten demo window smoke tests; fmt, clippy, and rustdoc.
This commit is contained in:
0xrsydn
parent
ab625dc55d
commit
a9493d4cc6
11 changed files with 418 additions and 26 deletions
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@ -22,6 +22,8 @@ mod instruction_tests;
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#[cfg(test)]
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mod load_alias_tests;
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#[cfg(test)]
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mod open_bus_tests;
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#[cfg(test)]
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mod status_tests;
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#[cfg(test)]
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mod tests;
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@ -200,7 +202,7 @@ impl Cpu {
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fn execute_fetched(&mut self, instruction: u32, memory: &mut Memory) -> Result<(), CpuError> {
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// Record the executing instruction, not an operand's pipelined PC value.
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// Always clear the access context, including on diagnostic errors.
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memory.begin_cpu_access(self.pc());
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memory.begin_cpu_access(self.pc(), self.instruction_set);
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let result = self.execute_instruction(instruction, memory);
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memory.end_cpu_access();
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result
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304
crates/gba-core/src/cpu/open_bus_tests.rs
Normal file
304
crates/gba-core/src/cpu/open_bus_tests.rs
Normal file
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@ -0,0 +1,304 @@
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//! Original regressions for the ARM unused-memory open-bus subset.
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use super::*;
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use crate::{
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dma::{DmaError, DMA_BASE, DMA_STRIDE},
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io::TIMER_BASE,
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machine::{Machine, MachineError, StepKind},
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memory::{BIOS_SIZE, ROM_START},
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timing::{bus_cycles, AccessKind, AccessWidth},
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};
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const DATA: u32 = 0xf233_80a5;
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const UNUSED: u32 = 0x8000_0000;
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const RAM: u32 = 0x0200_0100;
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const LDR: u32 = 0xe590_1000; // LDR r1, [r0]
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fn memory(instruction: u32) -> Memory {
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let words = [instruction, 0xe1a0_0000, DATA];
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Memory::new(words.into_iter().flat_map(u32::to_le_bytes).collect()).unwrap()
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}
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#[test]
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fn arm_unused_ranges_return_pc_plus_eight_not_address_mirrors() {
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for address in [
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0x0000_4000,
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0x0000_fffc,
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0x00ff_fffc,
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0x0100_0000,
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0x01ff_fffc,
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0x1000_0000,
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0x1800_0000,
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0x8000_0000,
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0xffff_fffc,
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] {
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let mut bus = memory(LDR);
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = address;
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let mut expected = cpu.clone();
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expected.registers[1] = DATA;
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expected.registers[15] += 4;
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu, expected, "{address:#010x}");
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// Inspection outside CPU execution remains strict, including every lane.
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for low in 0..4 {
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assert_eq!(
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bus.read8(address + low),
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Err(MemoryError::Unmapped(address + low))
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);
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}
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assert_eq!(bus.read16(address), Err(MemoryError::Unmapped(address)));
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assert_eq!(bus.read32(address), Err(MemoryError::Unmapped(address)));
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}
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}
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#[test]
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fn open_bus_loads_select_lanes_rotate_and_sign_extend_normally() {
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// Independent expectations for bytes [a5,80,33,f2].
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for (instruction, values) in [
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(LDR, [0xf233_80a5, 0xa5f2_3380, 0x80a5_f233, 0x3380_a5f2]),
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(0xe5d0_1000, [0xa5, 0x80, 0x33, 0xf2]), // LDRB
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(0xe1d0_10b0, [0x80a5, 0xa500_0080, 0xf233, 0x3300_00f2]), // LDRH
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(0xe1d0_10d0, [0xffff_ffa5, 0xffff_ff80, 0x33, 0xffff_fff2]), // LDRSB
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(
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0xe1d0_10f0,
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[0xffff_80a5, 0xffff_ff80, 0xffff_f233, 0xffff_fff2],
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), // LDRSH
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] {
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for (low, value) in values.into_iter().enumerate() {
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let mut bus = memory(instruction);
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED + low as u32;
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cpu.apply_status(0xb000_00df, Mode::System);
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let mut expected = cpu.clone();
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expected.registers[1] = value;
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expected.registers[15] += 4;
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let timing = cpu.step_timed(&mut bus).unwrap();
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assert_eq!(cpu, expected, "{instruction:#010x}, lane {low}");
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assert_eq!(timing.data_cycles, 1);
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assert_eq!(timing.internal_cycles, 1);
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assert_eq!(timing.code_cycles, 8); // ROM boundary; no extra lookahead cost
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assert_eq!(bus.cycles(), 0);
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}
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}
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}
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#[test]
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fn prefetch_snapshot_uses_the_executing_region_and_rom_window() {
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for pc in [
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0x100,
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RAM,
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0x0300_0100,
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0x0500_0100,
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0x0600_0100,
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0x0700_0100,
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ROM_START,
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0x0a00_0000,
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0x0c00_0000,
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] {
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let mut bus = if pc < BIOS_SIZE as u32 {
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let mut bios = vec![0; BIOS_SIZE];
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bios[pc as usize..pc as usize + 4].copy_from_slice(&LDR.to_le_bytes());
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bios[pc as usize + 8..pc as usize + 12].copy_from_slice(&DATA.to_le_bytes());
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Memory::with_bios(vec![], bios).unwrap()
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} else if pc >= ROM_START {
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memory(LDR)
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} else {
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let mut bus = Memory::new(vec![]).unwrap();
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bus.write32(pc, LDR).unwrap();
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bus.write32(pc + 8, DATA).unwrap();
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bus
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};
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let mut cpu = Cpu::new(pc);
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cpu.registers[0] = UNUSED;
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let timing = cpu.step_timed(&mut bus).unwrap();
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assert_eq!(cpu.registers[1], DATA, "{pc:#010x}");
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assert_eq!(timing.data_cycles, 1);
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assert_eq!(
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timing.code_cycles,
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bus_cycles(0, pc, AccessWidth::Word, AccessKind::Sequential)
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);
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}
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}
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#[test]
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fn rrx_offset_load_preserves_carry_and_writes_back_the_high_address() {
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let mut bus = memory(0xe7b1_2060); // LDR r2, [r1, r0, RRX]!
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let mut cpu = Cpu::new(ROM_START);
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cpu.flags.carry = true;
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[0], 0);
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assert_eq!(cpu.registers[1], UNUSED);
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assert_eq!(cpu.registers[2], DATA);
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assert_eq!(cpu.cpsr(), 0x2000_001f);
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}
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#[test]
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fn block_loads_share_one_prefetch_word_and_single_load_aliases_still_work() {
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let mut bus = memory(0xe8b0_000e); // LDMIA r0!, {r1-r3}
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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let timing = cpu.step_timed(&mut bus).unwrap();
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assert_eq!(&cpu.registers[1..4], &[DATA; 3]);
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assert_eq!(cpu.registers[0], UNUSED + 12);
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assert_eq!(timing.data_cycles, 3);
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let mut bus = memory(0xe5b0_0004); // LDR r0, [r0, #4]!
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[0], DATA);
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}
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#[test]
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fn pc_load_uses_old_pc_snapshot_then_resamples_at_the_branch_target() {
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let mut bus = memory(0xe590_f000); // LDR pc, [r0]
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bus.write32(RAM, 0xe590_f000).unwrap();
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bus.write32(RAM + 8, RAM + 0x40).unwrap();
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bus.write32(RAM + 0x40, LDR).unwrap();
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bus.write32(RAM + 0x48, DATA).unwrap();
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let mut cpu = Cpu::new(RAM);
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cpu.registers[0] = UNUSED;
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), RAM + 0x40);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[1], DATA);
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}
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#[test]
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fn missing_prefetch_only_errors_when_an_unused_read_needs_it() {
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for size in 4..12 {
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let mut rom = vec![0; size];
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rom[..4].copy_from_slice(&LDR.to_le_bytes());
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let mut bus = Memory::new(rom).unwrap();
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bus.write32(RAM, DATA).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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let before = cpu.clone();
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assert_eq!(
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cpu.step_timed(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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assert_eq!(cpu, before);
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assert_eq!(bus.read32(UNUSED), Err(MemoryError::Unmapped(UNUSED)));
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cpu.registers[0] = RAM;
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let timing = cpu.step_timed(&mut bus).unwrap();
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assert_eq!(cpu.registers[1], DATA);
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assert_eq!(timing.data_cycles, 6); // No trace leaked from failed step.
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}
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// PC+8 is itself unused. Do not recursively manufacture a prefetch word.
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let mut bios = vec![0; BIOS_SIZE];
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bios[BIOS_SIZE - 8..BIOS_SIZE - 4].copy_from_slice(&LDR.to_le_bytes());
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let mut bus = Memory::with_bios(vec![], bios).unwrap();
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let mut cpu = Cpu::new(BIOS_SIZE as u32 - 8);
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cpu.registers[0] = UNUSED;
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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}
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#[test]
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fn skipped_loads_need_no_prefetch_and_charge_no_data_cycles() {
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let mut bus = Memory::new((LDR & 0x0fff_ffff).to_le_bytes().to_vec()).unwrap(); // LDREQ
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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let timing = cpu.step_timed(&mut bus).unwrap();
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assert_eq!(cpu.pc(), ROM_START + 4);
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assert_eq!(cpu.registers[1], 0);
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assert_eq!(timing.data_cycles, 0);
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assert_eq!(timing.internal_cycles, 0);
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}
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#[test]
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fn missing_bios_rom_save_and_unsupported_io_reads_remain_errors() {
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for address in [
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0,
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0x3ffc,
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0x0400_00e0,
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ROM_START + 12,
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0x0e00_0000,
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0x0fff_fffc,
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] {
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let mut bus = memory(LDR);
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = address;
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(address)))
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);
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assert_eq!(cpu, before);
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assert_eq!(bus.read32(UNUSED), Err(MemoryError::Unmapped(UNUSED)));
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}
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}
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#[test]
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fn thumb_reads_and_unused_instruction_fetches_do_not_reuse_arm_context() {
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let mut bus = memory(LDR);
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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cpu.step(&mut bus).unwrap();
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// A successful ARM read must not leave a context for later fetches or Thumb.
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let mut invalid = Cpu::new(UNUSED);
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assert_eq!(
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invalid.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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bus.write16(RAM, 0x6801).unwrap(); // Thumb LDR r1, [r0]
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cpu.registers[15] = RAM;
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cpu.instruction_set = InstructionSet::Thumb;
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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assert_eq!(cpu, before);
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}
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#[test]
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fn unused_stores_and_swaps_remain_atomic_diagnostics() {
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for instruction in [0xe580_1000, 0xe5c0_1000, 0xe1c0_10b0, 0xe100_1092] {
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let mut bus = memory(instruction); // STR, STRB, STRH, SWP
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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cpu.registers[1] = 0x1234;
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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assert_eq!(cpu, before);
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assert_eq!(bus.read32(UNUSED), Err(MemoryError::Unmapped(UNUSED)));
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}
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}
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#[test]
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fn machine_charges_one_data_access_and_dma_does_not_inherit_cpu_context() {
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let mut bus = memory(LDR);
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bus.write32(TIMER_BASE, 0x0080_0000).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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let mut machine = Machine::new(cpu, bus);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers[1], DATA);
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assert_eq!(machine.cycles(), 10); // 8 code + 1 data + 1 internal
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 10);
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let before = machine.cpu().clone();
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let timing = machine.last_timing();
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// DMA3 exposes all 28 source address bits. Save memory is still unsupported.
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let dma = DMA_BASE + 3 * DMA_STRIDE;
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machine.memory_mut().write32(dma, 0x0e00_0000).unwrap();
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machine.memory_mut().write32(dma + 4, RAM).unwrap();
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machine.memory_mut().write32(dma + 8, 0x8400_0001).unwrap();
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assert_eq!(
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machine.step(),
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Err(MachineError::Dma(DmaError::Memory {
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channel: 3,
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error: MemoryError::Unmapped(0x0e00_0000),
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}))
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);
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), 10);
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assert_eq!(machine.last_timing(), timing);
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assert_eq!(machine.memory().read32(RAM).unwrap(), 0);
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}
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@ -1,6 +1,7 @@
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use std::{cell::Cell, error::Error, fmt};
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use crate::{
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cpu::InstructionSet,
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display::{DisplayPosition, CYCLES_PER_LINE, HBLANK_START, VISIBLE_LINES},
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dma::{DmaError, DMA_BASE, DMA_END},
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input::Buttons,
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@ -52,8 +53,15 @@ fn vram_index(address: u32) -> usize {
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}
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}
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#[derive(Clone, Copy)]
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struct CpuAccess {
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pc: u32,
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arm_prefetch: Option<u32>,
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}
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/// Work/video/palette RAM, OAM, cartridge ROM, optional BIOS, and supported I/O.
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/// BIOS read protection and open-bus behavior are not modeled.
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/// ARM data reads from unused memory return a PC+8 snapshot when available.
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/// BIOS protection, Thumb open bus, and DMA bus latches are not modeled.
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pub struct Memory {
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external_ram: Vec<u8>,
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internal_ram: Vec<u8>,
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@ -65,7 +73,7 @@ pub struct Memory {
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io: Io,
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cycles: u64,
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data_timing: Cell<Option<DataTiming>>,
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cpu_access: Option<u32>,
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cpu_access: Option<CpuAccess>,
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scanline_capture: Option<video::capture::Capture>,
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sprite_pipeline: pipeline::SpritePipeline,
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}
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@ -317,9 +325,25 @@ impl Memory {
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self.io.next_event_cycles()
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}
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pub(crate) fn begin_cpu_access(&mut self, pc: u32) {
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pub(crate) fn begin_cpu_access(&mut self, pc: u32, instruction_set: InstructionSet) {
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debug_assert!(self.cpu_access.is_none());
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self.cpu_access = Some(pc);
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// Sample before execution, without data timing or open-bus recursion.
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// Missing lookahead bytes must not fail an instruction that never uses them.
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let arm_prefetch = match instruction_set {
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InstructionSet::Arm => self.snapshot_arm_prefetch(pc),
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InstructionSet::Thumb => None,
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};
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self.cpu_access = Some(CpuAccess { pc, arm_prefetch });
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}
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fn snapshot_arm_prefetch(&self, pc: u32) -> Option<u32> {
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let mut bytes = [0; 4];
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for (offset, byte) in bytes.iter_mut().enumerate() {
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*byte = self
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.read_mapped_byte(pc.wrapping_add(8 + offset as u32))
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.ok()?;
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}
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Some(u32::from_le_bytes(bytes))
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}
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pub(crate) fn end_cpu_access(&mut self) {
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@ -328,7 +352,8 @@ impl Memory {
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fn can_write_power_control(&self) -> bool {
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// Bare memory writes are host/debug setup. CPU code must execute in BIOS.
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self.cpu_access.is_none_or(|pc| pc < BIOS_SIZE as u32)
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self.cpu_access
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.is_none_or(|access| access.pc < BIOS_SIZE as u32)
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}
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/// Current scanline position and frame/VBlank event counters.
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@ -390,6 +415,16 @@ impl Memory {
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// Multi-byte reads use this helper to avoid charging each byte as a bus access.
|
||||
fn read_byte(&self, address: u32) -> Result<u8, MemoryError> {
|
||||
if matches!(address, 0x0000_4000..=0x01ff_ffff | 0x1000_0000..=0xffff_ffff) {
|
||||
if let Some(word) = self.cpu_access.and_then(|access| access.arm_prefetch) {
|
||||
return Ok((word >> ((address & 3) * 8)) as u8);
|
||||
}
|
||||
}
|
||||
self.read_mapped_byte(address)
|
||||
}
|
||||
|
||||
// Strict lookup for host access, instruction fetches, and prefetch snapshots.
|
||||
fn read_mapped_byte(&self, address: u32) -> Result<u8, MemoryError> {
|
||||
match address >> 24 {
|
||||
0x00 => self
|
||||
.bios
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue