feat(bios): implement selective RegisterRamReset service

Execute SWI 0x01 through original ARM code. Clear selected work RAM, palette RAM, VRAM, and OAM; force blank; reset supported display, DMA, timer, and interrupt registers through normal bus writes. Preserve caller state and excluded BIOS work RAM apart from the common SWI frame.

Reject serial/sound reset flags before display or reset writes. Document the supported subset, timer counter behavior, DMA ordering, and RAM caller hazards. Add fifteen tests covering memory flags and boundaries, I/O defaults, rendering, register preservation, hidden device latches, diagnostics, and device progress.

Validated on Darwin arm64: 720 default and 709 core-only tests in debug and release; formatting, Clippy, rustdoc, ten native window smoke tests, and CPU/timer demos pass.
This commit is contained in:
0xrsydn 2026-10-05 15:48:32 +07:00
commit a8944d1d5f
5 changed files with 657 additions and 15 deletions

View file

@ -26,6 +26,8 @@ mod differential;
mod huffman;
#[path = "bios/lz77.rs"]
mod lz77;
#[path = "bios/ram_reset.rs"]
mod ram_reset;
#[path = "bios/reset.rs"]
mod reset;
#[path = "bios/run_length.rs"]
@ -229,7 +231,7 @@ fn vblank_wait_halts_dispatches_irq_and_returns_through_original_code() {
#[test]
fn unsupported_services_fail_at_an_explicit_instruction_trap() {
for service in [1, 3, 0x0d, 0x19, 0xff] {
for service in [3, 0x0d, 0x19, 0xff] {
let (mut machine, _) = call(service, false, [0, 0, 0]);
let error = (0..100)
.find_map(|_| machine.step().err())