feat(timing): implement nominal Game Pak opcode prefetch
This commit is contained in:
0xrsydn
parent
7f3ebd3a5d
commit
8f22092e06
25 changed files with 1062 additions and 124 deletions
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@ -142,7 +142,7 @@ fn sampling_has_no_timing_or_history_side_effects_and_never_uses_data_fallback()
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bios[8..12].copy_from_slice(&WORD.to_le_bytes());
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let mut memory = Memory::with_bios(vec![], bios).unwrap();
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memory.cpu_resume_nonsequential = true;
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memory.begin_cpu_timing();
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memory.begin_cpu_timing(false);
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let fetch = memory.fetch_instruction(8, InstructionSet::Arm);
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memory.fetch_instruction(0x0300_0000, InstructionSet::Thumb);
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assert_eq!(memory.end_cpu_timing(true), StepTiming::default());
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304
crates/gba-core/src/memory/prefetch_tests.rs
Normal file
304
crates/gba-core/src/memory/prefetch_tests.rs
Normal file
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@ -0,0 +1,304 @@
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//! Original integration checks. Expected cycles are explicit, not computed by the queue.
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use super::{timing_event_tests::prepared, *};
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use crate::{
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cpu::Cpu,
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dma::DMA_STRIDE,
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io::{HALTCNT, IE, IME, TIMER_BASE, WAITCNT},
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machine::{Machine, StepKind},
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timing::TimingEvent,
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};
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const NOP: u32 = 0xe1a0_0000;
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const RAM: u32 = 0x0300_1000;
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fn enable(memory: &mut Memory) {
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memory.write16(WAITCNT, 0x4000).unwrap();
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}
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fn dma(memory: &mut Memory, source: u32, destination: u32) {
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let base = DMA_BASE + 3 * DMA_STRIDE;
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memory.write32(base, source).unwrap();
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memory.write32(base + 4, destination).unwrap();
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memory.write32(base + 8, 0x8400_0001).unwrap();
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}
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#[test]
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fn ram_loads_and_internal_work_reduce_the_following_fetch_despite_cpu_n_kind() {
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for (thumb, instruction, address, expected) in [
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(false, 0xe591_0000, RAM, 4), // 6 ROM cycles minus RAM 1 and load 1I.
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(false, 0xe591_0000, 0x0200_1000, 1), // EWRAM 6 plus load 1I.
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(true, 0x6808, RAM, 1), // 3 ROM cycles minus RAM 1 and load 1I.
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(false, 0xe1a0_0312, RAM, 5), // Register shift supplies 1I.
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(true, 0x4090, RAM, 2), // Thumb register shift supplies 1I.
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] {
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let (mut cpu, mut memory) = prepared(thumb, &[instruction, NOP], &[(1, address)]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, expected);
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assert!(matches!(memory.last_cpu_timing.unwrap().events()[0],
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TimingEvent::Code { kind: AccessKind::NonSequential, cycles, .. } if cycles == expected));
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assert_eq!(memory.cycles(), 0);
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}
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}
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#[test]
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fn rom_data_cancels_the_queue_and_charges_its_last_cycle_stall() {
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// An EWRAM load leaves seven free cycles. The following hit advances one more
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// cycle before ROM data cancels the active third halfword.
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let (mut cpu, mut memory) = prepared(
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false,
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&[0xe591_0000, 0xe592_0000, NOP],
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&[(1, 0x0200_1000), (2, ROM_START)],
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);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap(); // Seven idle-bus cycles: two entries and one cycle of the third.
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let timing = cpu.step_timed(&mut memory).unwrap(); // Hit adds one more cycle: remaining=1.
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assert_eq!(timing.code_cycles, 1);
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assert_eq!(timing.data_cycles, 9); // Raw N+S=8, cancellation=1.
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assert_eq!(timing.internal_cycles, 1);
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, 8);
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}
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#[test]
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fn branches_can_match_the_head_or_cancel_a_partial_fetch() {
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for (instruction, expected) in [(0xea00_0001, 18), (0xea00_0010, 20)] {
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let (mut cpu, mut memory) = prepared(false, &[instruction], &[]);
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enable(&mut memory);
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, expected);
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, 6);
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}
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let (mut cpu, mut memory) = prepared(false, &[0xe591_f000], &[(1, RAM)]);
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memory.write32(RAM, ROM_START + 0x300).unwrap();
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enable(&mut memory);
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let timing = cpu.step_timed(&mut memory).unwrap();
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assert_eq!(timing.code_cycles, 21); // Source 6, cancelled target 9, second target 6.
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assert_eq!(timing.data_cycles + timing.internal_cycles, 2);
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}
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#[test]
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fn swi_return_keeps_queue_ownership_separate_from_saved_instruction_state() {
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for thumb in [false, true] {
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let swi = if thumb { 0xdf00 } else { 0xef00_0000 };
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let nop = if thumb { 0x46c0 } else { NOP };
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let (mut cpu, mut memory) = prepared(thumb, &[swi, nop], &[]);
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// Original one-instruction BIOS handler: MOVS pc,lr restores the saved state.
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memory.bios.as_mut().unwrap()[8..12].copy_from_slice(&0xe1b0_f00e_u32.to_le_bytes());
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enable(&mut memory);
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let state = cpu.instruction_set();
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let return_pc = cpu.pc() + if thumb { 2 } else { 4 };
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assert_eq!(
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cpu.step_timed(&mut memory).unwrap().code_cycles,
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if thumb { 5 } else { 8 }
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);
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assert_eq!(cpu.pc(), 8);
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assert_eq!(
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cpu.step_timed(&mut memory).unwrap().code_cycles,
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if thumb { 9 } else { 15 }
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);
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assert_eq!((cpu.pc(), cpu.instruction_set()), (return_pc, state));
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assert_eq!(
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cpu.step_timed(&mut memory).unwrap().code_cycles,
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if thumb { 3 } else { 6 }
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);
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assert_eq!(memory.cycles(), 0);
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}
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}
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#[test]
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fn timed_and_cpu_only_execution_commit_the_same_queue_without_device_clocks() {
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for thumb in [false, true] {
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let load = if thumb { 0x6808 } else { 0xe591_0000 };
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let nop = if thumb { 0x46c0 } else { NOP };
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let (mut timed, mut a) = prepared(thumb, &[load, nop, load, nop], &[(1, 0x0200_1000)]);
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let (mut plain, mut b) = prepared(thumb, &[load, nop, load, nop], &[(1, 0x0200_1000)]);
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enable(&mut a);
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enable(&mut b);
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for _ in 0..4 {
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let timing = timed.step_timed(&mut a).unwrap();
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plain.step(&mut b).unwrap();
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assert_eq!(timed, plain);
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assert_eq!(a.gamepak_prefetch, b.gamepak_prefetch);
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assert_eq!(timing, b.last_cpu_timing.unwrap().total);
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assert_eq!((a.cycles(), b.cycles()), (0, 0));
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}
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}
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}
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#[test]
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fn failures_discard_source_and_partial_data_progress() {
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for (bad, address) in [(0xe591_0000, 0x0e00_0000), (0xe8b1_0005, IME)] {
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let (mut cpu, mut memory) = prepared(false, &[NOP, bad], &[(1, address)]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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let queue = memory.gamepak_prefetch;
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let previous = memory.last_cpu_timing.unwrap().events();
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let before = cpu.clone();
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for _ in 0..2 {
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assert!(cpu.step_timed(&mut memory).is_err());
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assert_eq!(cpu, before);
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assert_eq!(memory.gamepak_prefetch, queue);
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assert_eq!(memory.last_cpu_timing.unwrap().events(), previous);
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assert!(memory.cpu_timing.get().is_none());
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}
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}
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}
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#[test]
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fn background_work_never_reads_missing_rom_bytes_or_fails_a_branch_early() {
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let mut memory = Memory::new(0xea00_003e_u32.to_le_bytes().to_vec()).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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enable(&mut memory);
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, 20);
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memory.advance_halt_cycles(1000); // Background addresses are beyond the file.
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let queue = memory.gamepak_prefetch;
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assert!(cpu.step_timed(&mut memory).is_err());
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assert_eq!(memory.gamepak_prefetch, queue);
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}
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#[test]
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fn host_access_and_clock_only_updates_do_not_advance_or_consume_the_queue() {
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let (mut cpu, mut memory) = prepared(false, &[NOP, NOP], &[]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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let queue = memory.gamepak_prefetch;
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memory.read32(ROM_START).unwrap();
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memory.write32(RAM, NOP).unwrap();
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memory.advance_cycles(1000);
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assert_eq!(memory.gamepak_prefetch, queue);
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, 6);
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}
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#[test]
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fn debugger_invalidation_discards_queued_timing_on_success() {
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let (mut cpu, mut memory) = prepared(false, &[0xe591_0000, NOP], &[(1, 0x0200_1000)]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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cpu.invalidate_pipeline();
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, 6); // Cold nominal S, not a hit.
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}
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#[test]
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fn cpu_waitcnt_write_resets_after_the_old_source_and_data_costs() {
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for new in [0, 0x4018, 0x4001, 0x4800] {
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let (mut cpu, mut memory) = prepared(false, &[0xe581_0000, NOP], &[(0, new), (1, WAITCNT)]);
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enable(&mut memory);
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let old = cpu.step_timed(&mut memory).unwrap();
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assert_eq!((old.code_cycles, old.data_cycles), (6, 1));
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assert_eq!(memory.waitcnt(), new as u16);
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let expected = match new {
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0 => 8, // Disabled: CPU N request.
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0x4018 => 5, // Changed waits reset queue: new N+S.
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_ => 5, // SRAM/PHI keep queue: 6 minus the store's free cycle.
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};
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, expected);
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}
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}
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#[test]
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fn host_byte_and_dma_waitcnt_writes_apply_queue_configuration() {
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let (mut cpu, mut memory) = prepared(false, &[NOP, NOP, NOP], &[]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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memory.write8(WAITCNT, 0x18).unwrap();
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, 4);
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memory.write32(RAM, 0).unwrap();
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dma(&mut memory, RAM, WAITCNT);
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memory.step_dma().unwrap().unwrap();
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assert_eq!(memory.waitcnt(), 0);
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assert_eq!(cpu.step_timed(&mut memory).unwrap().code_cycles, 8);
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}
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#[test]
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fn ram_dma_advances_the_queue_and_rom_dma_cancels_it_before_cpu_resume() {
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for (source, destination, expected_dma, expected_cpu) in [
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(RAM, RAM + 4, 4, 2), // Startup 2 + RAM 1+1 gives four free cycles.
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(0x0200_1000, RAM, 9, 1), // EWRAM gives a complete word.
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(ROM_START, RAM, 12, 8), // Startup leaves remaining=1: ROM data stalls one cycle.
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] {
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let (mut cpu, mut memory) = prepared(false, &[NOP, NOP], &[]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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dma(&mut memory, source, destination);
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let (_, timing) = memory.step_dma().unwrap().unwrap();
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assert_eq!(timing.total(), expected_dma);
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assert_eq!(memory.cycles(), u64::from(expected_dma));
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assert_eq!(
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cpu.step_timed(&mut memory).unwrap().code_cycles,
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expected_cpu
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);
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assert!(!memory.cpu_resume_nonsequential);
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}
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}
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#[test]
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fn failed_dma_preserves_queue_and_clocks() {
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for (source, destination) in [(0x0e00_0000, RAM), (RAM, ROM_START)] {
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let (mut cpu, mut memory) = prepared(false, &[NOP], &[]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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let queue = memory.gamepak_prefetch;
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dma(&mut memory, source, destination);
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assert!(memory.step_dma().is_err());
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assert_eq!(memory.gamepak_prefetch, queue);
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assert_eq!(memory.cycles(), 0);
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assert!(!memory.cpu_resume_nonsequential);
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}
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}
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#[test]
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fn machine_advances_prefetch_once_and_halt_progresses_while_stop_freezes() {
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let (cpu, mut memory) = prepared(false, &[0xe591_0000, NOP], &[(1, RAM)]);
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enable(&mut memory);
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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machine.step().unwrap();
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assert_eq!(machine.last_timing().code_cycles, 4); // Bulk device advance must not fill queue again.
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assert_eq!(machine.cycles(), 12);
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for stop in [false, true] {
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let (mut cpu, mut memory) = prepared(false, &[NOP], &[]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap();
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memory.write8(HALTCNT, if stop { 0x80 } else { 0 }).unwrap();
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let queue = memory.gamepak_prefetch;
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let mut machine = Machine::new(cpu, memory);
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assert_eq!(
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machine.step().unwrap(),
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if stop {
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StepKind::StopIdle
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} else {
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StepKind::HaltIdle
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}
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);
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if stop {
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assert_eq!(machine.memory().gamepak_prefetch, queue);
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assert_eq!(machine.cycles(), 0);
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} else {
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assert_ne!(machine.memory().gamepak_prefetch, queue);
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assert!(machine.cycles() > 0);
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}
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}
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}
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#[test]
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fn irq_source_uses_queued_code_and_bios_vector_fetches_advance_the_rom_stream() {
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let (mut cpu, mut memory) = prepared(false, &[0xe591_0000, NOP], &[(1, RAM)]);
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enable(&mut memory);
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cpu.step_timed(&mut memory).unwrap(); // Next word has two cycles of progress.
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memory.write16(IE, 8).unwrap();
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memory.write16(IME, 1).unwrap();
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memory.write32(TIMER_BASE, 0x00c0_ffff).unwrap();
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memory.advance_cycles(1);
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let mut machine = Machine::new(cpu, memory);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(machine.last_timing().code_cycles, 6); // Source 4 plus vector 1+1.
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let mut queue = machine.memory().gamepak_prefetch;
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let events = machine.memory().last_cpu_timing.unwrap().events();
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let TimingEvent::Code { address, .. } = events[0] else {
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panic!("missing source")
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};
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assert_eq!(
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queue.code(address + 4, AccessWidth::Word, AccessKind::Sequential),
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4
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);
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}
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@ -13,7 +13,11 @@ const THUMB: u32 = ROM_START + 0x180;
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const DATA: u32 = 0x0300_1000;
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const ARM_NOP: u32 = 0xe1a0_0000;
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fn prepared(thumb: bool, instructions: &[u32], operands: &[(usize, u32)]) -> (Cpu, Memory) {
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pub(super) fn prepared(
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thumb: bool,
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instructions: &[u32],
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operands: &[(usize, u32)],
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) -> (Cpu, Memory) {
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let mut operands = operands.to_vec();
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if thumb {
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operands.push((12, THUMB | 1));
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@ -210,7 +214,7 @@ fn swaps_and_register_shifts_place_internal_cycles_after_their_bus_work() {
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#[test]
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fn waitcnt_store_records_old_source_settings_and_next_step_records_new_settings() {
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for waitcnt in [0x18, 0x4018] {
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// Prefetch enable is still stored only.
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// Enabling prefetch does not arm a stream before the next ROM code fetch.
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let (mut cpu, mut memory) = prepared(
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false,
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&[0xe581_0000, ARM_NOP],
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