feat(timing): implement nominal Game Pak opcode prefetch
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25 changed files with 1062 additions and 124 deletions
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@ -156,7 +156,8 @@ impl Machine {
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/// generate FIQ. IRQ entry consumes a separate step and does not clear IF.
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/// CPU/DMA work uses nominal costs; HALT advances exactly to the next device event.
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/// CPU writes take effect before this bulk device update. Within-instruction
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/// register timing, prefetch, and IRQ synchronization delays are not modeled.
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/// register timing and IRQ synchronization delays are not modeled. Opcode
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/// prefetch follows ordered nominal CPU/DMA costs, not per-cycle arbitration.
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/// CPU/DMA diagnostics leave CPU, devices, and the clock unchanged for this step.
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/// Row-capture diagnostics are deferred to Memory::present_frame instead.
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pub fn step(&mut self) -> Result<StepKind, MachineError> {
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@ -173,7 +174,7 @@ impl Machine {
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idle_cycles: self.memory.next_event_cycles(),
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..StepTiming::default()
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};
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self.memory.advance_cycles(timing.total());
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self.memory.advance_halt_cycles(timing.total());
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self.last_timing = timing;
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return Ok(StepKind::HaltIdle);
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}
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