feat(cartridge): implement transactional Flash programming and erase
This commit is contained in:
0xrsydn
parent
2ea7164d9a
commit
8ded9bc90e
7 changed files with 452 additions and 20 deletions
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@ -7,7 +7,10 @@ mod flash;
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mod rtc;
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pub use calendar::{RtcDateTime, RtcError};
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use flash::Flash;
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pub use flash::{SaveDevice, SaveError, SAVE_END, SAVE_START};
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pub(crate) use flash::SaveMutation;
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pub use flash::{
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SaveDevice, SaveError, FLASH_ERASE_CYCLES, FLASH_PROGRAM_CYCLES, SAVE_END, SAVE_START,
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};
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use rtc::Rtc;
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pub const GPIO_DATA: u32 = 0x0800_00c4;
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@ -46,6 +49,20 @@ impl Cartridge {
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self.flash.is_some() && (SAVE_START..=SAVE_END).contains(&address)
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}
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pub(crate) fn advance(&mut self, cycles: u32) {
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if let Some(flash) = self.flash.as_mut() {
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flash.advance(cycles);
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}
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}
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pub(crate) fn save_unfinished(&self) -> bool {
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self.flash.is_some_and(Flash::unfinished)
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}
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pub(crate) fn take_save_mutation(&mut self) -> Option<SaveMutation> {
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self.flash.as_mut().and_then(Flash::take_mutation)
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}
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pub(crate) fn read_save8(&self, address: u32, image: &[u8]) -> Result<u8, MemoryError> {
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self.flash.expect("mapped save device").read(address, image)
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}
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@ -94,7 +111,12 @@ impl Cartridge {
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}
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/// Apply one access to a copy first. A rejected second halfword changes nothing.
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pub(crate) fn write(&mut self, address: u32, bytes: &[u8]) -> Result<(), MemoryError> {
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pub(crate) fn write(
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&mut self,
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address: u32,
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bytes: &[u8],
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image: &[u8],
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) -> Result<(), MemoryError> {
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if !self.mapped(address) {
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return Ok(()); // Non-cartridge accesses are validated by the bus.
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}
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@ -105,7 +127,7 @@ impl Cartridge {
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operation: "Flash non-byte write",
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});
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}
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return self.flash.as_mut().unwrap().write(address, bytes[0]);
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return self.flash.as_mut().unwrap().write(address, bytes[0], image);
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}
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let fail = |at, value, operation| MemoryError::UnsupportedIo {
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address: at,
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@ -1,18 +1,20 @@
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//! Bounded Macronix Flash identification, array reads, and 128 KiB banking.
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//! Program/erase commands remain diagnostic: this module cannot claim a completed save.
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//! Bounded Macronix Flash commands with nominal delayed program/erase completion.
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use crate::memory::MemoryError;
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use std::{error::Error, fmt};
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pub const SAVE_START: u32 = 0x0e00_0000;
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pub const SAVE_END: u32 = 0x0e00_ffff;
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/// Nominal simulation delays, not measured Macronix operation times.
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pub const FLASH_PROGRAM_CYCLES: u32 = 650;
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pub const FLASH_ERASE_CYCLES: u32 = 30000;
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub enum SaveDevice {
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#[default]
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None,
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/// Macronix ID 1CC2h. Array reads and identification only.
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/// Macronix ID 1CC2h, 64 KiB array.
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Flash64,
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/// Macronix ID 09C2h. Adds two 64 KiB banks; no programming or erase yet.
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/// Macronix ID 09C2h, two 64 KiB banks.
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Flash128,
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}
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@ -50,6 +52,21 @@ pub(super) struct Flash {
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phase: Phase,
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identify: bool,
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bank: u8,
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pending: Option<Pending>,
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub(crate) struct SaveMutation {
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pub(crate) start: usize,
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pub(crate) end: usize,
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pub(crate) value: u8,
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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struct Pending {
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mutation: SaveMutation,
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remaining: u32,
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poll: u32,
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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@ -58,6 +75,10 @@ enum Phase {
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Unlock,
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Command,
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Bank,
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Program,
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EraseUnlock,
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EraseCommand,
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EraseConfirm,
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}
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impl Flash {
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@ -67,6 +88,7 @@ impl Flash {
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phase: Phase::Ready,
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identify: false,
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bank: 0,
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pending: None,
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})
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}
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@ -76,6 +98,22 @@ impl Flash {
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pub(super) fn read(self, address: u32, image: &[u8]) -> Result<u8, MemoryError> {
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let offset = (address - SAVE_START) as usize;
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let index = usize::from(self.bank) * 0x10000 + offset;
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if let Some(pending) = self.pending {
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if pending.remaining != 0 {
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if address != pending.poll {
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return Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "Flash busy read outside polling address",
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});
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}
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// Bounded DQ7-only data polling. Toggle/error bits are not modeled.
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return Ok((pending.mutation.value ^ 0x80) & 0x80);
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}
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if (pending.mutation.start..pending.mutation.end).contains(&index) {
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return Ok(pending.mutation.value);
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}
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}
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if self.identify {
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return match offset {
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0 => Ok(0xc2),
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@ -90,10 +128,33 @@ impl Flash {
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}),
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};
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}
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Ok(image[usize::from(self.bank) * 0x10000 + offset])
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Ok(image[index])
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}
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pub(super) fn write(&mut self, address: u32, value: u8) -> Result<(), MemoryError> {
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pub(super) fn advance(&mut self, cycles: u32) {
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if let Some(pending) = self.pending.as_mut() {
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pending.remaining = pending.remaining.saturating_sub(cycles);
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}
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}
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pub(super) fn unfinished(self) -> bool {
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self.pending.is_some() || self.phase != Phase::Ready
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}
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pub(super) fn take_mutation(&mut self) -> Option<SaveMutation> {
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if self.pending.is_some_and(|p| p.remaining == 0) {
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self.pending.take().map(|p| p.mutation)
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} else {
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None
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}
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}
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pub(super) fn write(
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&mut self,
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address: u32,
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value: u8,
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image: &[u8],
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) -> Result<(), MemoryError> {
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let offset = address - SAVE_START;
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let error = |operation| MemoryError::UnsupportedIo {
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address,
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@ -101,9 +162,19 @@ impl Flash {
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operation,
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};
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let mut next = *self;
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if self.pending.is_some_and(|p| p.remaining != 0) {
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if self.device == SaveDevice::Flash64 && offset == 0x5555 && value == 0xf0 {
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next.pending = None;
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next.phase = Phase::Ready;
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*self = next;
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return Ok(());
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}
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return Err(error("Flash write during busy operation"));
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}
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// GBATEK documents direct reset for the 64 KiB chip. For 128 KiB, accept
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// only a redundant reset while already idle in array mode. No busy/ID exit is inferred.
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if offset == 0x5555
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if self.phase != Phase::Program
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&& offset == 0x5555
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&& value == 0xf0
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&& (self.device == SaveDevice::Flash64
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|| (self.phase == Phase::Ready && !self.identify))
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@ -129,8 +200,8 @@ impl Flash {
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}
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0xb0 if self.device == SaveDevice::Flash128 => Phase::Bank,
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0xb0 => return Err(error("Flash bank selection on 64 KiB device")),
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0xa0 => return Err(error("Flash byte programming")),
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0x80 => return Err(error("Flash erase setup")),
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0xa0 => Phase::Program,
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0x80 => Phase::EraseUnlock,
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_ => return Err(error("Flash command")),
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}
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}
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@ -139,6 +210,52 @@ impl Flash {
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Phase::Ready
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}
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Phase::Bank => return Err(error("Flash bank address/value")),
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Phase::Program => {
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if self.pending.is_some() {
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return Err(error("Flash completion awaiting commit"));
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}
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let index = usize::from(self.bank) * 0x10000 + offset as usize;
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if value & !image[index] != 0 {
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return Err(error(
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"Flash programming requires erase for zero-to-one bits",
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));
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}
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next.pending = Some(Pending {
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mutation: SaveMutation {
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start: index,
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end: index + 1,
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value,
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},
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remaining: FLASH_PROGRAM_CYCLES,
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poll: address,
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});
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Phase::Ready
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}
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Phase::EraseUnlock if offset == 0x5555 && value == 0xaa => Phase::EraseCommand,
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Phase::EraseCommand if offset == 0x2aaa && value == 0x55 => Phase::EraseConfirm,
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Phase::EraseConfirm => {
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if self.pending.is_some() {
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return Err(error("Flash completion awaiting commit"));
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}
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let (start, end, poll) = match value {
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0x10 if offset == 0x5555 => (0, self.device.capacity(), SAVE_START),
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0x30 if offset & 0xfff == 0 => {
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let start = usize::from(self.bank) * 0x10000 + offset as usize;
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(start, start + 0x1000, address)
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}
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_ => return Err(error("Flash erase confirmation/address")),
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};
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next.pending = Some(Pending {
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mutation: SaveMutation {
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start,
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end,
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value: 0xff,
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},
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remaining: FLASH_ERASE_CYCLES,
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poll,
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});
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Phase::Ready
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}
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_ => return Err(error("Flash unlock/reset sequence")),
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};
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}
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@ -12,6 +12,8 @@ mod fetch_tests;
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#[cfg(test)]
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mod flash_step_tests;
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#[cfg(test)]
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mod flash_write_tests;
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#[cfg(test)]
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mod irq_fetch_tests;
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mod iwram_bus;
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#[cfg(test)]
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@ -138,6 +140,8 @@ pub struct Memory {
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oam: Vec<u8>,
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rom: Vec<u8>,
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save_image: Vec<u8>,
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save_modified: bool,
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cartridge_elapsed: Cell<u32>,
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cartridge: Cartridge,
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cartridge_step: Cell<Option<Cartridge>>,
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bios: Option<Vec<u8>>,
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@ -170,6 +174,8 @@ impl Memory {
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oam: vec![0; 1024],
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rom,
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save_image: Vec::new(),
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save_modified: false,
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cartridge_elapsed: Cell::new(0),
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cartridge: Cartridge::default(),
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cartridge_step: Cell::new(None),
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bios: None,
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@ -218,6 +224,7 @@ impl Memory {
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"active cartridge transaction"
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);
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self.save_image = vec![0xff; device.capacity()];
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self.save_modified = false;
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self.cartridge.set_save_device(device);
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}
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@ -244,6 +251,7 @@ impl Memory {
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});
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}
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self.save_image.copy_from_slice(bytes);
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self.save_modified = false;
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self.cartridge.set_save_device(device);
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Ok(())
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}
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@ -272,6 +280,24 @@ impl Memory {
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self.cartridge.advance_rtc_seconds(seconds)
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}
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/// True after a completed Flash operation changed stored bytes since setup/load.
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pub fn save_modified(&self) -> bool {
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self.save_modified
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}
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/// A command or operation is incomplete. Hosts should not persist on exit in this state.
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pub fn save_write_pending(&self) -> bool {
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self.cartridge.save_unfinished()
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}
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fn commit_save_mutation(&mut self) {
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if let Some(effect) = self.cartridge.take_save_mutation() {
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let target = &mut self.save_image[effect.start..effect.end];
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self.save_modified |= target.iter().any(|&b| b != effect.value);
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target.fill(effect.value);
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}
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}
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fn cartridge_state(&self) -> Cartridge {
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self.cartridge_step.get().unwrap_or(self.cartridge)
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}
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@ -345,14 +371,21 @@ impl Memory {
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debug_assert!(self.timer_step.get().is_none());
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self.timer_step.set(Some(self.io.timer_step()));
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self.cartridge_step.set(Some(self.cartridge));
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self.cartridge_elapsed.set(0);
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}
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pub(crate) fn discard_timer_step(&self) {
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self.timer_step.set(None);
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self.cartridge_step.set(None);
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self.cartridge_elapsed.set(0);
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}
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fn advance_timer_step(&self, cycles: u32) {
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if let Some(mut cartridge) = self.cartridge_step.get() {
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cartridge.advance(cycles - self.cartridge_elapsed.get());
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self.cartridge_elapsed.set(cycles);
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self.cartridge_step.set(Some(cartridge));
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}
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if let Some(mut step) = self.timer_step.get() {
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step.advance_to(cycles);
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self.timer_step.set(Some(step));
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@ -370,11 +403,15 @@ impl Memory {
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.cartridge_step
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.take()
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.expect("active cartridge transaction");
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self.commit_save_mutation();
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self.cartridge_elapsed.set(0);
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// Staged devices already reached this boundary. Advance remaining devices exactly once.
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self.advance_running_cycles_with_timers(cycles, false);
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}
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fn advance_running_cycles(&mut self, cycles: u32) {
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self.cartridge.advance(cycles);
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self.commit_save_mutation();
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self.advance_running_cycles_with_timers(cycles, true);
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}
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@ -930,8 +967,6 @@ impl Memory {
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) -> Result<(), MemoryError> {
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let index = self.write_index::<N>(address, access)?;
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Self::validate_io_values(&mut self.audio_state(), address, &bytes)?;
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let mut cartridge = self.cartridge_state();
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cartridge.write(address, &bytes)?;
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self.record_access(
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address,
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match N {
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@ -941,6 +976,8 @@ impl Memory {
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_ => unreachable!("unsupported bus width"),
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},
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);
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let mut cartridge = self.cartridge_state();
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cartridge.write(address, &bytes, &self.save_image)?;
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if cartridge.mapped(address) {
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if self.cartridge_step.get().is_some() {
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self.cartridge_step.set(Some(cartridge));
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@ -1150,6 +1187,8 @@ impl Memory {
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let mut cartridge = self.cartridge_state();
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let timing = self.cpu_timing.get();
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let devices = self.timer_step.get();
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let cartridge_step = self.cartridge_step.get();
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let cartridge_elapsed = self.cartridge_elapsed.get();
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// Preflight ordered data phases on temporary device/timing copies.
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// A serial request can finish before a later control write reaches the bus.
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let validation = (|| {
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@ -1157,7 +1196,7 @@ impl Memory {
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self.write_index::<4>(address, self.write_access())?;
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let bytes = value.to_le_bytes();
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Self::validate_io_values(&mut audio, address, &bytes)?;
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cartridge.write(address, &bytes)?;
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cartridge.write(address, &bytes, &self.save_image)?;
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self.record_access(address, AccessWidth::Word);
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if Serial::mapped(address) {
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if let Some(mut step) = self.timer_step.get() {
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@ -1174,6 +1213,8 @@ impl Memory {
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})();
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self.cpu_timing.set(timing);
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self.timer_step.set(devices);
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self.cartridge_step.set(cartridge_step);
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self.cartridge_elapsed.set(cartridge_elapsed);
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validation?;
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for &(address, value) in writes {
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// The map cannot change between validation and these writes.
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@ -73,7 +73,7 @@ fn work_ram_byte_loads_observe_selected_id_with_save_bus_costs() {
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}
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#[test]
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fn rejected_programming_and_rom_execution_reads_roll_back_cpu_and_command_state() {
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fn rejected_commands_and_rom_execution_reads_roll_back_cpu_and_command_state() {
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for thumb in [false, true] {
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for read in [false, true] {
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let (cpu, mut memory) = prepared(
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@ -84,7 +84,7 @@ fn rejected_programming_and_rom_execution_reads_roll_back_cpu_and_command_state(
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(false, true) => 0xe5d10000,
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(true, true) => 0x7808,
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}],
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&[(0, 0xa0), (1, if read { SAVE_START } else { HI })],
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&[(0, 0x42), (1, if read { SAVE_START } else { HI })],
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);
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unlocked(&mut memory);
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let before = memory.cartridge;
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@ -94,7 +94,7 @@ fn rejected_programming_and_rom_execution_reads_roll_back_cpu_and_command_state(
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assert!(error.to_string().contains(if read {
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"outside work RAM"
|
||||
} else {
|
||||
"programming"
|
||||
"Flash command"
|
||||
}));
|
||||
assert_eq!(machine.step(), Err(error));
|
||||
assert_eq!(machine.cpu(), &cpu);
|
||||
|
|
|
|||
95
crates/gba-core/src/memory/flash_write_tests.rs
Normal file
95
crates/gba-core/src/memory/flash_write_tests.rs
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
//! Original completion-at-bus-phase and mutation rollback checks.
|
||||
use super::{timing_event_tests::prepared, *};
|
||||
use crate::{
|
||||
cartridge::{SaveDevice, FLASH_PROGRAM_CYCLES as PROGRAM, SAVE_START as BASE},
|
||||
io::SOUNDBIAS,
|
||||
machine::Machine,
|
||||
};
|
||||
fn setup(m: &mut Memory) {
|
||||
m.set_save_device(SaveDevice::Flash128);
|
||||
m.write8(BASE + 0x5555, 0xaa).unwrap();
|
||||
m.write8(BASE + 0x2aaa, 0x55).unwrap();
|
||||
m.write8(BASE + 0x5555, 0xa0).unwrap();
|
||||
}
|
||||
#[test]
|
||||
fn arm_and_thumb_program_start_excludes_preceding_bus_cycles() {
|
||||
for thumb in [false, true] {
|
||||
let (cpu, mut m) = prepared(
|
||||
thumb,
|
||||
&[if thumb { 0x7008 } else { 0xe5c10000 }],
|
||||
&[(0, 0x12), (1, BASE)],
|
||||
);
|
||||
setup(&mut m);
|
||||
let mut machine = Machine::new(cpu, m);
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.memory().save_image().unwrap()[0], 255);
|
||||
machine.memory_mut().advance_cycles(PROGRAM - 1);
|
||||
assert_eq!(machine.memory().save_image().unwrap()[0], 255);
|
||||
machine.memory_mut().advance_cycles(1);
|
||||
assert_eq!(machine.memory().save_image().unwrap()[0], 0x12);
|
||||
assert!(machine.memory().save_modified());
|
||||
}
|
||||
}
|
||||
#[test]
|
||||
fn failed_block_load_restores_completion_and_dirty_state() {
|
||||
let (cpu, mut m) = prepared(false, &[0xe8910005], &[(1, SOUNDBIAS)]);
|
||||
setup(&mut m);
|
||||
m.write8(BASE, 0x12).unwrap();
|
||||
m.advance_cycles(PROGRAM - 7);
|
||||
let controller = m.cartridge;
|
||||
let mut machine = Machine::new(cpu, m);
|
||||
for _ in 0..2 {
|
||||
assert!(machine.step().is_err());
|
||||
assert_eq!(machine.memory().cartridge, controller);
|
||||
assert_eq!(machine.memory().save_image().unwrap()[0], 255);
|
||||
assert!(!machine.memory().save_modified());
|
||||
assert_eq!(machine.cycles(), u64::from(PROGRAM - 7));
|
||||
}
|
||||
machine.memory_mut().advance_cycles(7);
|
||||
assert_eq!(machine.memory().save_image().unwrap()[0], 0x12);
|
||||
}
|
||||
#[test]
|
||||
fn read_at_completion_uses_staged_overlay_and_read_before_completion_sees_busy() {
|
||||
for elapsed in [PROGRAM - 7, PROGRAM - 6] {
|
||||
let (mut cpu, mut m) = prepared(false, &[0xe12fff12], &[(1, BASE), (2, 0x03001000)]);
|
||||
for i in 0..8 {
|
||||
m.write32(
|
||||
0x03001000 + i * 4,
|
||||
if i == 0 { 0xe5d10000 } else { 0xe1a00000 },
|
||||
)
|
||||
.unwrap();
|
||||
}
|
||||
cpu.step(&mut m).unwrap();
|
||||
setup(&mut m);
|
||||
m.write8(BASE, 0).unwrap();
|
||||
m.advance_cycles(elapsed);
|
||||
let mut machine = Machine::new(cpu, m);
|
||||
machine.step().unwrap();
|
||||
assert_eq!(
|
||||
machine.cpu().registers()[0],
|
||||
if elapsed == PROGRAM - 6 { 0 } else { 0x80 }
|
||||
);
|
||||
assert_eq!(machine.memory().save_image().unwrap()[0], 0);
|
||||
}
|
||||
}
|
||||
#[test]
|
||||
fn preflight_and_discard_cannot_apply_save_mutations() {
|
||||
let (_, mut m) = prepared(false, &[0xe1a00000], &[]);
|
||||
setup(&mut m);
|
||||
m.write8(BASE, 0x12).unwrap();
|
||||
m.advance_cycles(PROGRAM - 1);
|
||||
let before = m.cartridge;
|
||||
m.begin_timer_step();
|
||||
m.advance_timer_step(1);
|
||||
assert_eq!(m.read8(BASE).unwrap(), 0x12);
|
||||
assert_eq!(m.save_image().unwrap()[0], 255);
|
||||
let shadow = m.cartridge_step.get();
|
||||
let elapsed = m.cartridge_elapsed.get();
|
||||
assert!(m.write_words(&[(0x02000000, 42), (BASE, 0)]).is_err());
|
||||
assert_eq!(m.cartridge_step.get(), shadow);
|
||||
assert_eq!(m.cartridge_elapsed.get(), elapsed);
|
||||
assert_eq!(m.read32(0x02000000).unwrap(), 0);
|
||||
m.discard_timer_step();
|
||||
assert_eq!(m.cartridge, before);
|
||||
assert!(!m.save_modified());
|
||||
}
|
||||
|
|
@ -122,8 +122,8 @@ fn bank_selection_covers_every_byte_and_survives_id_mode() {
|
|||
fn unsupported_commands_and_bad_bank_values_are_retryable_without_data_changes() {
|
||||
for device in [SaveDevice::Flash64, SaveDevice::Flash128] {
|
||||
for (byte, message) in [
|
||||
(0xa0, "programming"),
|
||||
(0x80, "erase setup"),
|
||||
(0x42, "Flash command"),
|
||||
(0x30, "Flash command"),
|
||||
(0x10, "Flash command"),
|
||||
] {
|
||||
let mut bus = memory(device);
|
||||
|
|
|
|||
157
crates/gba-core/tests/flash_write.rs
Normal file
157
crates/gba-core/tests/flash_write.rs
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
//! Original byte-program/erase probes. Nominal delays are not physical chip timings.
|
||||
use gba_core::{
|
||||
cartridge::{
|
||||
SaveDevice, FLASH_ERASE_CYCLES as ERASE, FLASH_PROGRAM_CYCLES as PROGRAM,
|
||||
SAVE_START as BASE,
|
||||
},
|
||||
io::{HALTCNT, IF},
|
||||
memory::Memory,
|
||||
};
|
||||
const HI: u32 = BASE + 0x5555;
|
||||
const LO: u32 = BASE + 0x2aaa;
|
||||
fn bus(device: SaveDevice) -> Memory {
|
||||
let mut m = Memory::new(vec![]).unwrap();
|
||||
m.set_save_device(device);
|
||||
m
|
||||
}
|
||||
fn command(m: &mut Memory, command: u8) {
|
||||
m.write8(HI, 0xaa).unwrap();
|
||||
m.write8(LO, 0x55).unwrap();
|
||||
m.write8(HI, command).unwrap();
|
||||
}
|
||||
fn program(m: &mut Memory, address: u32, value: u8) {
|
||||
command(m, 0xa0);
|
||||
m.write8(address, value).unwrap();
|
||||
}
|
||||
fn erase(m: &mut Memory, address: u32, confirm: u8) {
|
||||
command(m, 0x80);
|
||||
m.write8(HI, 0xaa).unwrap();
|
||||
m.write8(LO, 0x55).unwrap();
|
||||
m.write8(address, confirm).unwrap();
|
||||
}
|
||||
fn bank(m: &mut Memory, index: u8) {
|
||||
command(m, 0xb0);
|
||||
m.write8(BASE, index).unwrap();
|
||||
}
|
||||
#[test]
|
||||
fn every_byte_value_programs_after_delay_without_touching_neighbors_or_other_bank() {
|
||||
let mut m = bus(SaveDevice::Flash128);
|
||||
for b in 0..2 {
|
||||
bank(&mut m, b);
|
||||
for value in 0..=255 {
|
||||
let address = BASE + u32::from(value);
|
||||
program(&mut m, address, value);
|
||||
assert!(m.save_write_pending());
|
||||
assert_eq!(m.read8(address).unwrap(), (value ^ 0x80) & 0x80);
|
||||
assert_eq!(
|
||||
m.save_image().unwrap()[usize::from(b) * 65536 + usize::from(value)],
|
||||
255
|
||||
);
|
||||
m.advance_cycles(PROGRAM - 1);
|
||||
assert_eq!(m.read8(address).unwrap(), (value ^ 0x80) & 0x80);
|
||||
m.advance_cycles(1);
|
||||
assert_eq!(m.read8(address).unwrap(), value);
|
||||
assert!(!m.save_write_pending());
|
||||
}
|
||||
}
|
||||
let image = m.save_image().unwrap();
|
||||
for b in 0..2 {
|
||||
for (i, &v) in image[b * 65536..(b + 1) * 65536].iter().enumerate() {
|
||||
assert_eq!(v, if i < 256 { i as u8 } else { 255 });
|
||||
}
|
||||
}
|
||||
assert!(m.save_modified());
|
||||
assert_eq!(m.read16(IF).unwrap(), 0);
|
||||
}
|
||||
#[test]
|
||||
fn sector_and_chip_erases_have_exact_scope_and_wait_for_completion() {
|
||||
for device in [SaveDevice::Flash64, SaveDevice::Flash128] {
|
||||
let mut m = bus(device);
|
||||
m.load_save_image(&vec![0; device.capacity()]).unwrap();
|
||||
if device == SaveDevice::Flash128 {
|
||||
bank(&mut m, 1);
|
||||
}
|
||||
erase(&mut m, BASE + 0xf000, 0x30);
|
||||
assert_eq!(m.read8(BASE + 0xf000).unwrap(), 0);
|
||||
m.advance_cycles(ERASE - 1);
|
||||
assert!(m.save_image().unwrap().iter().all(|&b| b == 0));
|
||||
m.advance_cycles(1);
|
||||
let start = device.capacity() - 4096;
|
||||
assert!(m.save_image().unwrap()[..start].iter().all(|&b| b == 0));
|
||||
assert!(m.save_image().unwrap()[start..].iter().all(|&b| b == 255));
|
||||
erase(&mut m, HI, 0x10);
|
||||
m.advance_cycles(ERASE);
|
||||
assert!(m.save_image().unwrap().iter().all(|&b| b == 255));
|
||||
}
|
||||
}
|
||||
#[test]
|
||||
fn data_at_unlock_address_is_not_mistaken_for_reset_and_zero_to_one_requires_erase() {
|
||||
let mut m = bus(SaveDevice::Flash64);
|
||||
program(&mut m, HI, 0xf0);
|
||||
m.advance_cycles(PROGRAM);
|
||||
assert_eq!(m.read8(HI).unwrap(), 0xf0);
|
||||
program(&mut m, HI, 0x80);
|
||||
m.advance_cycles(PROGRAM);
|
||||
assert_eq!(m.read8(HI).unwrap(), 0x80);
|
||||
command(&mut m, 0xa0);
|
||||
let error = m.write8(HI, 0xff).unwrap_err();
|
||||
assert!(error.to_string().contains("requires erase"));
|
||||
assert_eq!(m.write8(HI, 0xff), Err(error));
|
||||
m.write8(HI, 0).unwrap();
|
||||
m.advance_cycles(PROGRAM);
|
||||
assert_eq!(m.read8(HI).unwrap(), 0);
|
||||
}
|
||||
#[test]
|
||||
fn busy_access_limits_and_64_reset_are_atomic_without_fabricated_completion() {
|
||||
for device in [SaveDevice::Flash64, SaveDevice::Flash128] {
|
||||
let mut m = bus(device);
|
||||
program(&mut m, BASE + 123, 0x12);
|
||||
assert!(m.read8(BASE + 124).is_err());
|
||||
let error = m.write8(HI, 0xaa).unwrap_err();
|
||||
assert_eq!(m.write8(HI, 0xaa), Err(error));
|
||||
if device == SaveDevice::Flash64 {
|
||||
m.write8(HI, 0xf0).unwrap();
|
||||
m.advance_cycles(PROGRAM);
|
||||
assert_eq!(m.read8(BASE + 123).unwrap(), 255);
|
||||
assert!(!m.save_modified());
|
||||
} else {
|
||||
assert!(m.write8(HI, 0xf0).is_err());
|
||||
m.advance_cycles(PROGRAM);
|
||||
assert_eq!(m.read8(BASE + 123).unwrap(), 0x12);
|
||||
}
|
||||
}
|
||||
}
|
||||
#[test]
|
||||
fn invalid_erase_sequences_preserve_data_and_can_be_retried() {
|
||||
let mut m = bus(SaveDevice::Flash128);
|
||||
m.load_save_image(&vec![0; 131072]).unwrap();
|
||||
command(&mut m, 0x80);
|
||||
assert!(m.write8(LO, 0x55).is_err());
|
||||
m.write8(HI, 0xaa).unwrap();
|
||||
m.write8(LO, 0x55).unwrap();
|
||||
for (at, val) in [(BASE + 1, 0x30), (BASE, 0x10), (HI, 0x90)] {
|
||||
let err = m.write8(at, val).unwrap_err();
|
||||
assert_eq!(m.write8(at, val), Err(err));
|
||||
assert!(m.save_image().unwrap().iter().all(|&b| b == 0));
|
||||
}
|
||||
m.write8(BASE, 0x30).unwrap();
|
||||
m.advance_cycles(ERASE);
|
||||
assert!(m.save_image().unwrap()[..4096].iter().all(|&b| b == 255));
|
||||
}
|
||||
#[test]
|
||||
fn halt_clocks_nominal_operations_stop_freezes_them_and_setup_resets_dirty_state() {
|
||||
let mut m = bus(SaveDevice::Flash128);
|
||||
program(&mut m, BASE, 0);
|
||||
m.write8(HALTCNT, 0).unwrap();
|
||||
m.advance_cycles(PROGRAM);
|
||||
assert!(m.save_modified());
|
||||
assert_eq!(m.read8(BASE).unwrap(), 0);
|
||||
m.load_save_image(&vec![255; 131072]).unwrap();
|
||||
assert!(!m.save_modified());
|
||||
program(&mut m, BASE, 1);
|
||||
m.write8(HALTCNT, 0x80).unwrap();
|
||||
m.advance_cycles(PROGRAM);
|
||||
assert!(m.save_write_pending());
|
||||
assert!(!m.save_modified());
|
||||
assert_eq!(m.read8(BASE).unwrap(), 0x80);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue