feat(cartridge): add explicit Flash identification and banked reads
This commit is contained in:
0xrsydn
parent
fce222eea2
commit
8b3b7ae62d
23 changed files with 1042 additions and 52 deletions
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@ -3,8 +3,11 @@
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use crate::memory::MemoryError;
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mod calendar;
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mod flash;
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mod rtc;
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pub use calendar::{RtcDateTime, RtcError};
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use flash::Flash;
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pub use flash::{SaveDevice, SaveError, SAVE_END, SAVE_START};
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use rtc::Rtc;
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pub const GPIO_DATA: u32 = 0x0800_00c4;
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@ -23,13 +26,28 @@ pub enum CartridgeHardware {
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub(crate) struct Cartridge {
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gpio: Option<Gpio>,
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flash: Option<Flash>,
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}
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impl Cartridge {
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pub(crate) fn new(hardware: CartridgeHardware) -> Self {
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Self {
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gpio: (hardware == CartridgeHardware::Rtc).then(Gpio::default),
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}
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pub(crate) fn set_hardware(&mut self, hardware: CartridgeHardware) {
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self.gpio = (hardware == CartridgeHardware::Rtc).then(Gpio::default);
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}
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pub(crate) fn set_save_device(&mut self, device: SaveDevice) {
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self.flash = Flash::new(device);
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}
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pub(crate) fn save_device(&self) -> SaveDevice {
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self.flash.map_or(SaveDevice::None, Flash::device)
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}
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pub(crate) fn save_mapped(&self, address: u32) -> bool {
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self.flash.is_some() && (SAVE_START..=SAVE_END).contains(&address)
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}
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pub(crate) fn read_save8(&self, address: u32, image: &[u8]) -> Result<u8, MemoryError> {
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self.flash.expect("mapped save device").read(address, image)
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}
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pub(crate) fn rtc_datetime(&self) -> Option<RtcDateTime> {
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@ -56,13 +74,14 @@ impl Cartridge {
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}
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pub(crate) fn mapped(&self, address: u32) -> bool {
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self.gpio.is_some() && (GPIO_DATA..GPIO_CONTROL + 2).contains(&address)
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self.save_mapped(address)
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|| (self.gpio.is_some() && (GPIO_DATA..GPIO_CONTROL + 2).contains(&address))
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}
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/// Disabled reads expose the supplied ROM bytes, not a zero-filled replacement.
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pub(crate) fn read8(&self, address: u32) -> Option<u8> {
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let gpio = self.gpio?;
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if !self.mapped(address) || !gpio.readable {
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if !(GPIO_DATA..GPIO_CONTROL + 2).contains(&address) || !gpio.readable {
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return None;
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}
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let value = match address & !1 {
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@ -79,6 +98,15 @@ impl Cartridge {
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if !self.mapped(address) {
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return Ok(()); // Non-cartridge accesses are validated by the bus.
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}
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if self.save_mapped(address) {
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if bytes.len() != 1 {
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return Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "Flash non-byte write",
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});
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}
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return self.flash.as_mut().unwrap().write(address, bytes[0]);
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}
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let fail = |at, value, operation| MemoryError::UnsupportedIo {
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address: at,
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value,
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148
crates/gba-core/src/cartridge/flash.rs
Normal file
148
crates/gba-core/src/cartridge/flash.rs
Normal file
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@ -0,0 +1,148 @@
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//! Bounded Macronix Flash identification, array reads, and 128 KiB banking.
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//! Program/erase commands remain diagnostic: this module cannot claim a completed save.
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use crate::memory::MemoryError;
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use std::{error::Error, fmt};
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pub const SAVE_START: u32 = 0x0e00_0000;
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pub const SAVE_END: u32 = 0x0e00_ffff;
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub enum SaveDevice {
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#[default]
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None,
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/// Macronix ID 1CC2h. Array reads and identification only.
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Flash64,
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/// Macronix ID 09C2h. Adds two 64 KiB banks; no programming or erase yet.
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Flash128,
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}
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impl SaveDevice {
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pub fn capacity(self) -> usize {
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match self {
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Self::None => 0,
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Self::Flash64 => 64 * 1024,
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Self::Flash128 => 128 * 1024,
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}
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}
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub enum SaveError {
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NoDevice,
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InvalidSize { expected: usize, actual: usize },
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}
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impl fmt::Display for SaveError {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match self {
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Self::NoDevice => f.write_str("no cartridge save device selected"),
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Self::InvalidSize { expected, actual } => write!(
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f,
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"save image size {actual}; expected exactly {expected} bytes"
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),
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}
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}
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}
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impl Error for SaveError {}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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pub(super) struct Flash {
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device: SaveDevice,
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phase: Phase,
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identify: bool,
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bank: u8,
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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enum Phase {
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Ready,
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Unlock,
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Command,
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Bank,
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}
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impl Flash {
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pub(super) fn new(device: SaveDevice) -> Option<Self> {
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(device != SaveDevice::None).then_some(Self {
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device,
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phase: Phase::Ready,
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identify: false,
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bank: 0,
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})
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}
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pub(super) fn device(self) -> SaveDevice {
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self.device
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}
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pub(super) fn read(self, address: u32, image: &[u8]) -> Result<u8, MemoryError> {
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let offset = (address - SAVE_START) as usize;
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if self.identify {
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return match offset {
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0 => Ok(0xc2),
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1 => Ok(if self.device == SaveDevice::Flash64 {
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0x1c
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} else {
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9
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}),
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_ => Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "Flash ID read outside manufacturer/device bytes",
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}),
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};
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}
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Ok(image[usize::from(self.bank) * 0x10000 + offset])
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}
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pub(super) fn write(&mut self, address: u32, value: u8) -> Result<(), MemoryError> {
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let offset = address - SAVE_START;
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let error = |operation| MemoryError::UnsupportedIo {
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address,
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value,
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operation,
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};
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let mut next = *self;
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// GBATEK documents direct reset for the 64 KiB chip. For 128 KiB, accept
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// only a redundant reset while already idle in array mode. No busy/ID exit is inferred.
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if offset == 0x5555
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&& value == 0xf0
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&& (self.device == SaveDevice::Flash64
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|| (self.phase == Phase::Ready && !self.identify))
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{
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next.identify = false;
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next.phase = Phase::Ready;
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} else {
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next.phase = match self.phase {
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Phase::Ready if offset == 0x5555 && value == 0xaa => Phase::Unlock,
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Phase::Unlock if offset == 0x2aaa && value == 0x55 => Phase::Command,
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Phase::Command if offset == 0x5555 => {
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if self.identify && value != 0xf0 {
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return Err(error("Flash command while in ID mode"));
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}
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match value {
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0x90 => {
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next.identify = true;
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Phase::Ready
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}
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0xf0 => {
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next.identify = false;
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Phase::Ready
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}
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0xb0 if self.device == SaveDevice::Flash128 => Phase::Bank,
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0xb0 => return Err(error("Flash bank selection on 64 KiB device")),
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0xa0 => return Err(error("Flash byte programming")),
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0x80 => return Err(error("Flash erase setup")),
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_ => return Err(error("Flash command")),
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}
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}
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Phase::Bank if offset == 0 && value < 2 => {
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next.bank = value;
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Phase::Ready
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}
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Phase::Bank => return Err(error("Flash bank address/value")),
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_ => return Err(error("Flash unlock/reset sequence")),
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};
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}
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*self = next;
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Ok(())
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}
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}
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@ -8,6 +8,8 @@ mod fetch;
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#[cfg(test)]
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mod fetch_tests;
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#[cfg(test)]
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mod flash_step_tests;
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#[cfg(test)]
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mod irq_fetch_tests;
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mod iwram_bus;
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#[cfg(test)]
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@ -27,7 +29,7 @@ use iwram_bus::IwramBus;
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use crate::{
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audio::{Audio, StereoLevel},
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cartridge::{Cartridge, CartridgeHardware, RtcDateTime, RtcError},
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cartridge::{Cartridge, CartridgeHardware, RtcDateTime, RtcError, SaveDevice, SaveError},
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cpu::InstructionSet,
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display::{DisplayPosition, CYCLES_PER_LINE, HBLANK_START, VISIBLE_LINES},
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dma::{DmaError, DMA_BASE, DMA_END},
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@ -53,6 +55,10 @@ pub enum MemoryError {
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Unaligned(u32),
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RomTooLarge(usize),
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InvalidBiosSize(usize),
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UnsupportedCartridgeAccess {
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address: u32,
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operation: &'static str,
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},
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UnsupportedIo {
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address: u32,
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value: u8,
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@ -63,6 +69,9 @@ pub enum MemoryError {
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impl fmt::Display for MemoryError {
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fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
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match self {
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Self::UnsupportedCartridgeAccess { address, operation } => {
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write!(f, "unsupported {operation} at {address:#010x}")
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}
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Self::UnsupportedIo {
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address,
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value,
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@ -122,6 +131,7 @@ pub struct Memory {
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video_ram: Vec<u8>,
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oam: Vec<u8>,
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rom: Vec<u8>,
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save_image: Vec<u8>,
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cartridge: Cartridge,
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cartridge_step: Cell<Option<Cartridge>>,
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bios: Option<Vec<u8>>,
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@ -153,6 +163,7 @@ impl Memory {
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video_ram: vec![0; VRAM_SIZE],
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oam: vec![0; 1024],
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rom,
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save_image: Vec::new(),
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cartridge: Cartridge::default(),
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cartridge_step: Cell::new(None),
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bios: None,
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@ -183,14 +194,52 @@ impl Memory {
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Ok(memory)
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}
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/// Replace optional cartridge hardware with its initial state. Call between machine steps.
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/// This never modifies the supplied ROM bytes or enables a host clock.
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/// Replace GPIO/RTC hardware with its initial state. Call between machine steps.
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/// Save hardware/data are preserved. This never modifies ROM bytes or enables a host clock.
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pub fn set_cartridge_hardware(&mut self, hardware: CartridgeHardware) {
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assert!(
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self.cartridge_step.get().is_none(),
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"active cartridge transaction"
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);
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self.cartridge = Cartridge::new(hardware);
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self.cartridge.set_hardware(hardware);
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}
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/// Replace save hardware and its array with erased bytes. GPIO/RTC state is unchanged.
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/// Call between machine steps; no file is loaded or written by the core.
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pub fn set_save_device(&mut self, device: SaveDevice) {
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assert!(
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self.cartridge_step.get().is_none(),
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"active cartridge transaction"
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);
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self.save_image = vec![0xff; device.capacity()];
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self.cartridge.set_save_device(device);
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}
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/// Inspect the complete save array, independently of ID mode and selected bank.
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pub fn save_image(&self) -> Option<&[u8]> {
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(self.cartridge.save_device() != SaveDevice::None).then_some(self.save_image.as_slice())
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}
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/// Replace the entire array and reset Flash command/bank state. RTC state is unchanged.
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/// A wrong length changes nothing. This setup API does not emulate programming.
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pub fn load_save_image(&mut self, bytes: &[u8]) -> Result<(), SaveError> {
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assert!(
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self.cartridge_step.get().is_none(),
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"active cartridge transaction"
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);
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let device = self.cartridge.save_device();
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if device == SaveDevice::None {
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return Err(SaveError::NoDevice);
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}
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if bytes.len() != device.capacity() {
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return Err(SaveError::InvalidSize {
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expected: device.capacity(),
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actual: bytes.len(),
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});
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}
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self.save_image.copy_from_slice(bytes);
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self.cartridge.set_save_device(device);
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Ok(())
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}
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/// Inspect the live calendar, not an in-progress serial read snapshot.
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@ -749,6 +798,16 @@ impl Memory {
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// Multi-byte reads use this helper to avoid charging each byte as a bus access.
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fn read_byte(&self, address: u32) -> Result<u8, MemoryError> {
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if self.cartridge_state().save_mapped(address)
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&& self
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.cpu_access
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.is_some_and(|access| !matches!(access.pc >> 24, 0x02 | 0x03))
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{
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return Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "Flash CPU read outside work RAM",
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});
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}
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if address >> 24 == 0x04 {
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if let Some(step) = self.timer_step.get() {
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if Serial::mapped(address) {
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@ -784,7 +843,11 @@ impl Memory {
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// Strict lookup for host access, instruction fetches, and prefetch snapshots.
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fn read_mapped_byte(&self, address: u32) -> Result<u8, MemoryError> {
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if let Some(value) = self.cartridge_state().read8(address) {
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let cartridge = self.cartridge_state();
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if cartridge.save_mapped(address) {
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return cartridge.read_save8(address, &self.save_image);
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}
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if let Some(value) = cartridge.read8(address) {
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return Ok(value);
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}
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match address >> 24 {
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@ -1001,6 +1064,15 @@ impl Memory {
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}
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Ok(0)
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}
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0x0e if self.cartridge_state().save_mapped(address) => {
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if N != 1 {
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return Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "Flash non-byte write",
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});
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}
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Ok(0)
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}
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_ => Err(MemoryError::Unmapped(address)),
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}
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}
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@ -1086,6 +1158,7 @@ impl Memory {
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if address & 1 != 0 {
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return Err(MemoryError::Unaligned(address));
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}
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self.validate_save_read_width(address)?;
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self.record_access(address, AccessWidth::Halfword);
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let value = u16::from_le_bytes([self.read_byte(address)?, self.read_byte(address + 1)?]);
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self.iwram_bus
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@ -1093,11 +1166,22 @@ impl Memory {
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Ok(value)
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}
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fn validate_save_read_width(&self, address: u32) -> Result<(), MemoryError> {
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if self.cartridge_state().save_mapped(address) {
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return Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "Flash non-byte read",
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});
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}
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Ok(())
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}
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/// The bus requires alignment; the CPU applies ARM7TDMI load rotation.
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pub fn read32(&self, address: u32) -> Result<u32, MemoryError> {
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if address & 3 != 0 {
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return Err(MemoryError::Unaligned(address));
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}
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self.validate_save_read_width(address)?;
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self.record_access(address, AccessWidth::Word);
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let value = u32::from_le_bytes([
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self.read_byte(address)?,
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|
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@ -62,6 +62,12 @@ impl Memory {
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if address & (width as u32 - 1) != 0 {
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return Err(MemoryError::Unaligned(address));
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}
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if self.cartridge_state().save_mapped(address) {
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return Err(MemoryError::UnsupportedCartridgeAccess {
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address,
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operation: "Flash instruction fetch",
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});
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}
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let mut bytes = [0; 4];
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for (offset, byte) in bytes[..width].iter_mut().enumerate() {
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*byte = self.read_mapped_byte(address.wrapping_add(offset as u32))?;
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|
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148
crates/gba-core/src/memory/flash_step_tests.rs
Normal file
148
crates/gba-core/src/memory/flash_step_tests.rs
Normal file
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@ -0,0 +1,148 @@
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//! Original Flash CPU bus phases, failed writes, fetch restrictions, and preflight checks.
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use super::{timing_event_tests::prepared, *};
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use crate::{
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cartridge::{SaveDevice, SAVE_START},
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cpu::Cpu,
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io::{IF, WAITCNT},
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machine::Machine,
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};
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const HI: u32 = SAVE_START + 0x5555;
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const LO: u32 = SAVE_START + 0x2aaa;
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fn unlocked(memory: &mut Memory) {
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memory.set_save_device(SaveDevice::Flash128);
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memory.write8(HI, 0xaa).unwrap();
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memory.write8(LO, 0x55).unwrap();
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}
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fn ram_reader(thumb: bool, base: u32) -> (Cpu, Memory) {
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let (mut cpu, mut memory) = prepared(
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false,
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&[0xe12fff12],
|
||||
&[(1, SAVE_START), (2, base | u32::from(thumb))],
|
||||
);
|
||||
for at in (0..32).step_by(4) {
|
||||
memory
|
||||
.write32(base + at, if thumb { 0x46c046c0 } else { 0xe1a00000 })
|
||||
.unwrap();
|
||||
}
|
||||
if thumb {
|
||||
memory.write16(base, 0x7808).unwrap();
|
||||
} else {
|
||||
memory.write32(base, 0xe5d10000).unwrap();
|
||||
}
|
||||
cpu.step(&mut memory).unwrap(); // BX from setup ROM into original RAM reader.
|
||||
(cpu, memory)
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn arm_and_thumb_flash_commands_commit_once_at_all_save_wait_settings() {
|
||||
for thumb in [false, true] {
|
||||
for (wait, cycles) in [5, 4, 3, 9].into_iter().enumerate() {
|
||||
let (cpu, mut memory) = prepared(
|
||||
thumb,
|
||||
&[if thumb { 0x7008 } else { 0xe5c10000 }],
|
||||
&[(0, 0x90), (1, HI)],
|
||||
);
|
||||
unlocked(&mut memory);
|
||||
memory.write16(WAITCNT, wait as u16).unwrap();
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.memory().read8(SAVE_START).unwrap(), 0xc2);
|
||||
assert_eq!(machine.last_timing().data_cycles, cycles);
|
||||
assert_eq!(machine.memory().read16(IF).unwrap(), 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn work_ram_byte_loads_observe_selected_id_with_save_bus_costs() {
|
||||
for thumb in [false, true] {
|
||||
for base in [0x02001000, 0x03001000] {
|
||||
for (wait, cycles) in [5, 4, 3, 9].into_iter().enumerate() {
|
||||
let (cpu, mut memory) = ram_reader(thumb, base);
|
||||
unlocked(&mut memory);
|
||||
memory.write8(HI, 0x90).unwrap();
|
||||
memory.write16(WAITCNT, wait as u16).unwrap();
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.cpu().registers()[0], 0xc2);
|
||||
assert_eq!(machine.last_timing().data_cycles, cycles);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn rejected_programming_and_rom_execution_reads_roll_back_cpu_and_command_state() {
|
||||
for thumb in [false, true] {
|
||||
for read in [false, true] {
|
||||
let (cpu, mut memory) = prepared(
|
||||
thumb,
|
||||
&[match (thumb, read) {
|
||||
(false, false) => 0xe5c10000,
|
||||
(true, false) => 0x7008,
|
||||
(false, true) => 0xe5d10000,
|
||||
(true, true) => 0x7808,
|
||||
}],
|
||||
&[(0, 0xa0), (1, if read { SAVE_START } else { HI })],
|
||||
);
|
||||
unlocked(&mut memory);
|
||||
let before = memory.cartridge;
|
||||
let mut machine = Machine::new(cpu, memory);
|
||||
let cpu = machine.cpu().clone();
|
||||
let error = machine.step().unwrap_err();
|
||||
assert!(error.to_string().contains(if read {
|
||||
"outside work RAM"
|
||||
} else {
|
||||
"programming"
|
||||
}));
|
||||
assert_eq!(machine.step(), Err(error));
|
||||
assert_eq!(machine.cpu(), &cpu);
|
||||
assert_eq!(machine.memory().cartridge, before);
|
||||
assert_eq!(machine.cycles(), 0);
|
||||
machine.memory_mut().write8(HI, 0x90).unwrap(); // Failure retained the accepted unlock prefix.
|
||||
assert_eq!(machine.memory().read8(SAVE_START).unwrap(), 0xc2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn staged_id_reads_and_discard_do_not_mutate_array_or_committed_controller() {
|
||||
let (_, mut memory) = prepared(false, &[0xe1a00000], &[]);
|
||||
unlocked(&mut memory);
|
||||
let before = memory.cartridge;
|
||||
memory.begin_timer_step();
|
||||
memory.write8(HI, 0x90).unwrap();
|
||||
assert_eq!(memory.read8(SAVE_START).unwrap(), 0xc2);
|
||||
assert_eq!(memory.cartridge, before);
|
||||
memory.discard_timer_step();
|
||||
assert_eq!(memory.read8(SAVE_START).unwrap(), 255);
|
||||
memory.write8(HI, 0x90).unwrap();
|
||||
memory.begin_timer_step();
|
||||
memory.write8(HI, 0xaa).unwrap();
|
||||
memory.write8(LO, 0x55).unwrap();
|
||||
memory.write8(HI, 0xf0).unwrap();
|
||||
assert_eq!(memory.read8(SAVE_START).unwrap(), 255);
|
||||
memory.discard_timer_step();
|
||||
assert_eq!(memory.read8(SAVE_START).unwrap(), 0xc2);
|
||||
assert!(memory.save_image().unwrap().iter().all(|&b| b == 255));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn instruction_fetch_and_block_word_access_cannot_bypass_byte_only_device() {
|
||||
let (_, mut memory) = prepared(false, &[0xe1a00000], &[]);
|
||||
unlocked(&mut memory);
|
||||
for state in [InstructionSet::Arm, InstructionSet::Thumb] {
|
||||
let error = memory
|
||||
.fetch_instruction(SAVE_START, state)
|
||||
.instruction
|
||||
.unwrap_err();
|
||||
assert!(error.to_string().contains("Flash instruction fetch"));
|
||||
}
|
||||
let before = memory.cartridge;
|
||||
assert!(memory
|
||||
.write_words(&[(0x02000000, 0x12345678), (SAVE_START, 0)])
|
||||
.is_err());
|
||||
assert_eq!(memory.read32(0x02000000).unwrap(), 0);
|
||||
assert_eq!(memory.cartridge, before);
|
||||
}
|
||||
|
|
@ -87,6 +87,8 @@ pub fn bus_cycles(waitcnt: u16, address: u32, width: AccessWidth, kind: AccessKi
|
|||
0
|
||||
}
|
||||
}
|
||||
// The supported save bus permits byte transfers only; N/S use the same SRAM waits.
|
||||
0x0e | 0x0f => 1 + [4, 3, 2, 8][usize::from(waitcnt & 3)],
|
||||
// BIOS, IWRAM, I/O, and OAM use a 32-bit bus. Other areas remain unmapped.
|
||||
_ => 1,
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,6 +10,30 @@ fn queue(waitcnt: u16) -> Prefetch {
|
|||
queue
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn save_wait_changes_preserve_the_queue_until_a_flash_data_access_cancels_it() {
|
||||
for (wait, raw) in [5, 4, 3, 9].into_iter().enumerate() {
|
||||
let mut q = queue(ENABLE);
|
||||
assert_eq!(
|
||||
q.code(PC, AccessWidth::Halfword, AccessKind::NonSequential),
|
||||
5
|
||||
);
|
||||
q.advance(2); // One cycle remains in the nominal three-cycle ROM halfword.
|
||||
let stream = q.stream;
|
||||
q.configure(ENABLE | wait as u16);
|
||||
assert_eq!(q.stream, stream);
|
||||
assert_eq!(
|
||||
q.data(0x0e005555, AccessWidth::Byte, AccessKind::NonSequential),
|
||||
raw + 1
|
||||
);
|
||||
assert_eq!(q.stream, None);
|
||||
assert_eq!(
|
||||
q.code(PC + 2, AccessWidth::Halfword, AccessKind::NonSequential),
|
||||
5
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn ready_and_in_progress_fetches_follow_all_rom_wait_settings_and_widths() {
|
||||
for window in 0..3 {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue