feat(memory): sample Thumb IWRAM refill targets
After successful refill instructions, sample the Thumb IWRAM target and target+2 halfwords to establish bus history. Share ARM/Thumb refill classification with nominal timing. Respect restored instruction state, completed data accesses, region limits, and diagnostic rollback; keep instruction execution and nominal costs unchanged. Add original regressions for ARM/Thumb BX, Thumb branches and BL, PC writes, stack/block PC loads, status-restoring returns, real SWI/IRQ returns, both target alignments, mirrors/wrap, captured sample ordering, load lanes, failure retention, BIOS isolation, and DMA invalidation. Document official ARM7TDMI refill evidence and the distinction from a full pipeline. Darwin arm64 validation: 917 workspace tests and 848 core/demo tests per debug/release profile; 39 preparation tests; native ROM windows in both profiles; ten graphics/window smoke modes; fmt, clippy, and rustdoc. Public ARM, Thumb, memory, and BIOS reports remain identical to prior passing results and between profiles. Cold startup, ARM-target refill history, and DMA-to-CPU ordering remain incomplete; no hardware-conformance or commercial-game claim.
This commit is contained in:
0xrsydn
parent
46af481487
commit
8b0f1a5ead
12 changed files with 566 additions and 35 deletions
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@ -24,6 +24,8 @@ mod instruction_tests;
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#[cfg(test)]
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mod iwram_open_bus_tests;
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#[cfg(test)]
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mod iwram_refill_tests;
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#[cfg(test)]
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mod load_alias_tests;
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#[cfg(test)]
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mod open_bus_tests;
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@ -211,14 +213,17 @@ impl Cpu {
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// Record the executing instruction, not an operand's pipelined PC value.
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// Always clear the access context, including on diagnostic errors.
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let pc = self.pc();
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let sequential_thumb =
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self.instruction_set == InstructionSet::Thumb && !self.thumb_refills(instruction);
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let refill = self.instruction_refills(instruction);
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let sequential_thumb = self.instruction_set == InstructionSet::Thumb && !refill;
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memory.begin_cpu_access(pc, self.instruction_set);
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let result = self.execute_instruction(instruction, memory);
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let sequential = sequential_thumb
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&& self.instruction_set == InstructionSet::Thumb
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&& self.pc() == pc.wrapping_add(2);
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memory.end_cpu_access(result.is_ok(), sequential);
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if result.is_ok() && refill {
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memory.refill_cpu_bus_history(self.pc(), self.instruction_set);
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}
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result
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}
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@ -295,7 +295,7 @@ fn failed_steps_discard_prefetch_history_before_retry() {
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}
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#[test]
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fn taken_control_flow_invalidates_history_even_when_target_is_fallthrough() {
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fn taken_control_flow_refills_history_even_when_target_is_fallthrough() {
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for branch in [0x4720, 0xe7ff, 0x46a7, 0xd0ff, 0xbd00] {
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// BX, B, MOV pc, BEQ, POP pc.
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let (mut cpu, mut bus) = program(CODE, &[SEED, branch, PROBE, 0x5566, 0x99aa]);
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@ -306,12 +306,8 @@ fn taken_control_flow_invalidates_history_even_when_target_is_fallthrough() {
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cpu.step(&mut bus).unwrap();
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), CODE + 4);
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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assert_eq!(cpu, before);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], 0x5566_99aa);
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}
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let (mut cpu, mut bus) = program(CODE, &[SEED, 0xd0ff, PROBE, 0x5566, 0x99aa]);
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cpu.flags.zero = false; // Untaken BEQ has no refill.
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425
crates/gba-core/src/cpu/iwram_refill_tests.rs
Normal file
425
crates/gba-core/src/cpu/iwram_refill_tests.rs
Normal file
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@ -0,0 +1,425 @@
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//! Original control-flow programs for Thumb IWRAM refill-lane snapshots.
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use super::*;
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use crate::{
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dma::{DMA_BASE, DMA_STRIDE},
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io::{IE, IME, TIMER_BASE},
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machine::{Machine, MachineError, StepKind},
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memory::{BIOS_SIZE, ROM_START},
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};
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const SOURCE: u32 = 0x0300_0100;
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const TARGET: u32 = 0x0300_0200;
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const STACK: u32 = 0x0300_1000;
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const UNUSED: u32 = 0x8000_0000;
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const PROBE: u16 = 0x6806; // LDR r6,[r0]
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const MARKER: u16 = 0x91ab;
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const LOOKAHEAD: u16 = 0xd234;
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fn target(bus: &mut Memory, pc: u32, instruction: u16) {
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for (index, half) in [instruction, MARKER, LOOKAHEAD, 0x5678]
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.into_iter()
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.enumerate()
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{
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bus.write16(pc + index as u32 * 2, half).unwrap();
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}
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}
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fn expected(pc: u32) -> u32 {
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if pc & 2 == 0 {
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0x91ab_d234
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} else {
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0xd234_91ab
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}
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}
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fn branch(source: u32, thumb: bool, destination: u32) -> (Cpu, Memory) {
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let instruction: u32 = if thumb { 0x46c0_4720 } else { 0xe12f_ff14 }; // BX r4
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let mut bus = if source < BIOS_SIZE as u32 {
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let mut bios = vec![0; BIOS_SIZE];
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bios[source as usize..source as usize + 4].copy_from_slice(&instruction.to_le_bytes());
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Memory::with_bios(vec![], bios).unwrap()
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} else if source == ROM_START {
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Memory::new(instruction.to_le_bytes().to_vec()).unwrap()
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} else {
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let mut bus = Memory::new(vec![]).unwrap();
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bus.write32(source, instruction).unwrap();
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bus
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};
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target(&mut bus, destination, PROBE);
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let mut cpu = Cpu::new(source);
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cpu.instruction_set = if thumb {
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InstructionSet::Thumb
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} else {
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InstructionSet::Arm
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};
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cpu.registers[0] = UNUSED;
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cpu.registers[4] = destination | 1;
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(cpu, bus)
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}
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#[test]
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fn arm_and_thumb_bx_establish_history_at_both_target_alignments_and_mirrors() {
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for source in [0x100, 0x0200_0100, SOURCE, ROM_START] {
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for thumb in [false, true] {
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for destination in [
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TARGET,
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TARGET + 2,
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TARGET + 0x8000,
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0x0300_7ffc,
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0x0300_7ffe,
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] {
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let (mut cpu, mut bus) = branch(source, thumb, destination);
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let status = cpu.cpsr() | 0xb000_00c0;
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cpu.apply_status(status, Mode::System);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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assert_eq!(cpu.instruction_set(), InstructionSet::Thumb);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], expected(destination));
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assert_eq!(cpu.cpsr(), status | 0x20);
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assert_eq!(cpu.registers[4], destination | 1);
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}
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}
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}
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}
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#[test]
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fn refill_samples_target_plus_two_at_branch_time_but_plus_four_on_arrival() {
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for destination in [TARGET, TARGET + 2] {
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let (mut cpu, mut bus) = branch(ROM_START, false, destination);
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cpu.step(&mut bus).unwrap();
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bus.write16(destination + 2, 0xeeee).unwrap();
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bus.write16(destination + 4, 0xabcd).unwrap();
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assert_eq!(bus.read16(destination + 2).unwrap(), 0xeeee);
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cpu.step(&mut bus).unwrap();
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assert_eq!(
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cpu.registers[6],
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if destination & 2 == 0 {
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0x91ab_abcd
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} else {
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0xabcd_91ab
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}
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);
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}
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}
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#[test]
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fn refill_history_supports_normal_load_lanes_rotation_and_sign_extension() {
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for destination in [TARGET, TARGET + 2] {
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let word = expected(destination);
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for (instruction, width, signed) in [
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(PROBE, 4, false),
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(0x7806, 1, false),
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(0x8806, 2, false),
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(0x5746, 1, true),
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(0x5f46, 2, true), // r5=0 offset, r6 result.
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] {
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for lane in 0..4 {
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let (mut cpu, mut bus) = branch(ROM_START, false, destination);
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target(&mut bus, destination, instruction);
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cpu.registers[0] += lane;
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cpu.step(&mut bus).unwrap();
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let byte = (word >> (lane * 8)) as u8;
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let half = (word >> ((lane & 2) * 8)) as u16;
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let value = match (width, signed) {
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(4, _) => word.rotate_right(lane * 8),
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(1, false) => u32::from(byte),
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(1, true) => byte as i8 as i32 as u32,
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(2, false) => u32::from(half).rotate_right((lane & 1) * 8),
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(2, true) if lane & 1 != 0 => byte as i8 as i32 as u32,
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(2, true) => half as i16 as i32 as u32,
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_ => unreachable!(),
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};
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let mut after = cpu.clone();
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after.registers[6] = value;
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after.registers[15] += 2;
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu, after);
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}
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}
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}
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}
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#[test]
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fn thumb_pc_writes_refill_after_data_loads_and_preserve_transfer_semantics() {
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for destination in [TARGET, TARGET + 2] {
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for instruction in [0x4720, 0x46a7, 0x44a7, 0xbd00, 0xbc00, 0xcc00] {
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// BX r4, MOV pc,r4, ADD pc,r4, POP {pc}, empty POP, empty LDM r4!.
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let (mut cpu, mut bus) = branch(SOURCE, true, destination);
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bus.write16(SOURCE, instruction).unwrap();
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bus.write32(STACK, destination).unwrap();
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cpu.registers[13] = STACK;
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cpu.registers[4] = match instruction {
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0xcc00 => STACK,
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0x44a7 => destination.wrapping_sub(SOURCE + 4),
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_ => destination | 1,
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};
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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assert_eq!(cpu.instruction_set(), InstructionSet::Thumb);
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if instruction == 0xbd00 {
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assert_eq!(cpu.registers[13], STACK + 4);
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}
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if instruction == 0xbc00 {
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assert_eq!(cpu.registers[13], STACK + 64);
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}
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if instruction == 0xcc00 {
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assert_eq!(cpu.registers[4], STACK + 64);
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(
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cpu.registers[6],
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expected(destination),
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"instruction={instruction:#x}"
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);
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}
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}
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}
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#[test]
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fn thumb_taken_branches_and_bl_suffix_establish_target_history() {
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for destination in [TARGET, TARGET + 2] {
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for kind in 0..3 {
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let (mut cpu, mut bus) = branch(SOURCE, true, destination);
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if kind == 2 {
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bus.write16(SOURCE, 0xf000).unwrap(); // BL prefix: high offset zero.
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bus.write16(SOURCE + 2, 0xf800 | ((destination - SOURCE - 4) / 2) as u16)
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.unwrap();
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), SOURCE + 2);
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} else {
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let offset = ((destination - SOURCE - 4) / 2) as u16;
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bus.write16(
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SOURCE,
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if kind == 0 {
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0xe000 | offset
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} else {
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0xd000 | offset
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},
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)
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.unwrap();
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cpu.flags.zero = true;
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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if kind == 2 {
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assert_eq!(cpu.registers[14], (SOURCE + 4) | 1);
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], expected(destination));
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}
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}
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}
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#[test]
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fn arm_exception_returns_use_saved_thumb_state_and_restored_banks() {
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for destination in [TARGET, TARGET + 2] {
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for mode in [Mode::User, Mode::System] {
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for instruction in [0xe1b0_f00e_u32, 0xe25e_f004, 0xe8fd_8004] {
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// MOVS pc,lr; SUBS pc,lr,#4; LDMIA sp!,{r2,pc}^.
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let mut bus = Memory::new(instruction.to_le_bytes().to_vec()).unwrap();
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target(&mut bus, destination, PROBE);
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bus.write32(STACK, 0xfeed_beef).unwrap();
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bus.write32(STACK + 4, destination).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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cpu.registers[13] = 0x0300_7000;
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cpu.registers[14] = 0x1234;
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cpu.enter_exception(Exception::SoftwareInterrupt);
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cpu.registers[15] = ROM_START;
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cpu.registers[13] = STACK;
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cpu.registers[14] = destination + if instruction == 0xe25e_f004 { 4 } else { 0 };
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let status = 0xa000_00e0 | mode as u32;
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cpu.set_spsr(status);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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assert_eq!(cpu.cpsr(), status);
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assert_eq!(cpu.registers[13], 0x0300_7000);
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assert_eq!(cpu.registers[14], 0x1234);
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if instruction == 0xe8fd_8004 {
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assert_eq!(cpu.registers[2], 0xfeed_beef);
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], expected(destination));
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cpu.switch_mode(Mode::Supervisor);
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assert_eq!(
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cpu.registers[13],
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STACK + if instruction == 0xe8fd_8004 { 8 } else { 0 }
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);
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}
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}
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}
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}
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#[test]
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fn real_swi_and_irq_returns_can_resume_thumb_iwram_with_known_lanes() {
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for irq in [false, true] {
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let destination = if irq { TARGET } else { TARGET + 2 };
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let mut bios = vec![0; BIOS_SIZE];
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bios[8..12].copy_from_slice(&0xe1b0_f00e_u32.to_le_bytes());
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bios[0x18..0x1c].copy_from_slice(&0xe25e_f004_u32.to_le_bytes());
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let mut bus = Memory::with_bios(vec![], bios).unwrap();
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target(&mut bus, destination, PROBE);
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if !irq {
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bus.write16(TARGET, 0xdf00).unwrap();
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}
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let mut cpu = Cpu::new(TARGET);
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cpu.instruction_set = InstructionSet::Thumb;
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cpu.registers[0] = UNUSED;
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let status = cpu.cpsr();
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let mut machine = Machine::new(cpu, bus);
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if irq {
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machine.memory_mut().write16(IE, 8).unwrap();
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machine.memory_mut().write16(IME, 1).unwrap();
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machine
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.memory_mut()
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.write32(TIMER_BASE, 0x00c0_ffff)
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.unwrap();
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machine.memory_mut().advance_cycles(1);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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machine.memory_mut().write16(IME, 0).unwrap(); // Keep this test to one IRQ entry.
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} else {
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machine.step().unwrap();
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}
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machine.step().unwrap(); // Execute the original ARM return handler.
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assert_eq!(machine.cpu().pc(), destination);
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assert_eq!(machine.cpu().cpsr(), status);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[6], expected(destination));
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}
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}
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#[test]
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fn failed_refill_instructions_preserve_cpu_and_preexisting_history() {
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for instruction in [0xe1b0_f00e_u32, 0xe8fd_8004] {
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let mut bus = Memory::new(instruction.to_le_bytes().to_vec()).unwrap();
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for (index, half) in [0x680a_u16, PROBE, 0x1111, LOOKAHEAD]
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.into_iter()
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.enumerate()
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{
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bus.write16(SOURCE + index as u32 * 2, half).unwrap();
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}
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bus.write32(STACK, 0x1234_abcd).unwrap();
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let mut paused = Cpu::new(SOURCE);
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paused.instruction_set = InstructionSet::Thumb;
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paused.registers[0] = UNUSED;
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paused.registers[1] = STACK;
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paused.step(&mut bus).unwrap(); // Seed sequential history with a word load.
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let mut failing = Cpu::at_reset();
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failing.registers[15] = ROM_START;
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failing.registers[13] = STACK;
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failing.registers[14] = TARGET;
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failing.set_spsr(0); // Invalid return mode; no refill must commit.
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let before = failing.clone();
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assert!(failing.step_timed(&mut bus).is_err());
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assert_eq!(failing, before);
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paused.step(&mut bus).unwrap();
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assert_eq!(paused.registers[6], 0xd234_abcd);
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}
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}
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#[test]
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fn cold_entry_region_crossings_and_unmapped_targets_do_not_invent_refill_history() {
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let mut bus = Memory::new(vec![]).unwrap();
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target(&mut bus, TARGET, PROBE);
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let mut cpu = Cpu::new(TARGET);
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cpu.instruction_set = InstructionSet::Thumb;
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cpu.registers[0] = UNUSED;
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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for destination in [0x03ff_fffc, 0x03ff_fffe, 0x0e00_0000] {
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let mut bus = Memory::new(0xe12f_ff14_u32.to_le_bytes().to_vec()).unwrap();
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if destination >> 24 == 3 {
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bus.write16(destination, PROBE).unwrap();
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}
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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cpu.registers[4] = destination | 1;
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cpu.step(&mut bus).unwrap(); // An unavailable target/refill never fails BX early.
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assert_eq!(cpu.pc(), destination);
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let before = cpu.clone();
|
||||
assert_eq!(
|
||||
cpu.step(&mut bus),
|
||||
Err(CpuError::Memory(MemoryError::Unmapped(
|
||||
if destination >> 24 == 3 {
|
||||
UNUSED
|
||||
} else {
|
||||
destination
|
||||
}
|
||||
)))
|
||||
);
|
||||
assert_eq!(cpu, before);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn target_pair_refill_does_not_replace_the_separate_bios_retained_word() {
|
||||
for destination in [TARGET, TARGET + 2] {
|
||||
let mut bios = vec![0; BIOS_SIZE];
|
||||
bios[0x100..0x104].copy_from_slice(&0xe12f_ff14_u32.to_le_bytes());
|
||||
bios[0x108..0x10c].copy_from_slice(&0x89ab_cdef_u32.to_le_bytes());
|
||||
let mut bus = Memory::with_bios(vec![], bios).unwrap();
|
||||
target(&mut bus, destination, PROBE);
|
||||
let mut cpu = Cpu::new(0x100);
|
||||
cpu.registers[4] = destination | 1;
|
||||
cpu.step(&mut bus).unwrap();
|
||||
cpu.step(&mut bus).unwrap(); // r0=0: protected BIOS read, not unused memory.
|
||||
assert_eq!(cpu.registers[6], 0x89ab_cdef);
|
||||
assert_eq!(bus.read32(0x108).unwrap(), 0x89ab_cdef);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn successful_dma_between_refill_and_target_execution_invalidates_refill_history() {
|
||||
let (cpu, mut bus) = branch(ROM_START, false, TARGET);
|
||||
bus.write32(STACK, 0x1234_abcd).unwrap();
|
||||
let mut machine = Machine::new(cpu, bus);
|
||||
machine.step().unwrap();
|
||||
let dma = DMA_BASE + 3 * DMA_STRIDE;
|
||||
machine.memory_mut().write32(dma, STACK).unwrap();
|
||||
machine.memory_mut().write32(dma + 4, 0x0200_0000).unwrap();
|
||||
machine.memory_mut().write32(dma + 8, 0x8400_0001).unwrap();
|
||||
assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 3 });
|
||||
let before = machine.cpu().clone();
|
||||
let timing = machine.last_timing();
|
||||
let cycles = machine.cycles();
|
||||
assert_eq!(
|
||||
machine.step(),
|
||||
Err(MachineError::Cpu(CpuError::Memory(MemoryError::Unmapped(
|
||||
UNUSED
|
||||
))))
|
||||
);
|
||||
assert_eq!(machine.cpu(), &before);
|
||||
assert_eq!(machine.last_timing(), timing);
|
||||
assert_eq!(machine.cycles(), cycles);
|
||||
assert_eq!(machine.cpu().pc(), TARGET);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn refill_snapshots_keep_existing_nominal_costs_and_timed_untimed_results() {
|
||||
for thumb in [false, true] {
|
||||
for destination in [TARGET, TARGET + 2] {
|
||||
let (cpu, mut bus) = branch(ROM_START, thumb, destination);
|
||||
bus.write32(TIMER_BASE, 0x0080_0000).unwrap();
|
||||
let mut machine = Machine::new(cpu, bus);
|
||||
let (mut untimed, mut bus) = branch(ROM_START, thumb, destination);
|
||||
for index in 0..2 {
|
||||
untimed.step(&mut bus).unwrap();
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.cpu(), &untimed);
|
||||
assert_eq!(
|
||||
machine.last_timing().code_cycles,
|
||||
if index == 0 { 3 } else { 1 }
|
||||
);
|
||||
assert_eq!(machine.last_timing().data_cycles, index);
|
||||
assert_eq!(machine.last_timing().internal_cycles, index);
|
||||
}
|
||||
assert_eq!(machine.cycles(), 6);
|
||||
assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 6);
|
||||
assert_eq!(bus.cycles(), 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
//! Nominal ARM7 instruction-cycle summaries, separate from instruction semantics.
|
||||
//! Data costs come from actual bus accesses. No speculative pipeline reads occur.
|
||||
//! Data costs come from actual bus accesses. Bus-history samples are separate from timing calculations.
|
||||
//! PC writes use target-region code costs, following GBATEK's cycle summary.
|
||||
|
||||
use super::{Cpu, CpuError, InstructionSet};
|
||||
|
|
@ -151,8 +151,11 @@ impl Cpu {
|
|||
|
||||
// Share the existing control-flow classification with bounded bus history.
|
||||
// A PC write can refill even when its target equals the sequential address.
|
||||
pub(super) fn thumb_refills(&self, instruction: u32) -> bool {
|
||||
self.thumb_summary(instruction).refill
|
||||
pub(super) fn instruction_refills(&self, instruction: u32) -> bool {
|
||||
match self.instruction_set {
|
||||
InstructionSet::Arm => self.arm_summary(instruction).refill,
|
||||
InstructionSet::Thumb => self.thumb_summary(instruction).refill,
|
||||
}
|
||||
}
|
||||
|
||||
fn thumb_summary(&self, instruction: u32) -> Summary {
|
||||
|
|
|
|||
|
|
@ -66,7 +66,8 @@ struct CpuAccess {
|
|||
/// Unused-memory reads use ARM PC+8 or supported region-dependent Thumb snapshots.
|
||||
/// Protected BIOS reads separately retain the snapshot from BIOS execution.
|
||||
/// Sequential Thumb IWRAM accesses retain addressed bus lanes transactionally.
|
||||
/// Refill history, a full fetch pipeline, and DMA bus latches are not modeled.
|
||||
/// Successful refills into Thumb IWRAM sample the target pair to establish history.
|
||||
/// A full fetch pipeline, ARM-target refill history, and DMA bus latches are not modeled.
|
||||
pub struct Memory {
|
||||
external_ram: Vec<u8>,
|
||||
internal_ram: Vec<u8>,
|
||||
|
|
@ -400,6 +401,24 @@ impl Memory {
|
|||
}
|
||||
}
|
||||
|
||||
/// Sample only the two target fetches of a completed refill into Thumb IWRAM.
|
||||
/// This updates bus history, not the CPU's instruction buffer or nominal costs.
|
||||
/// Incomplete or unsupported refills stay unknown without failing the branch early.
|
||||
pub(crate) fn refill_cpu_bus_history(&mut self, pc: u32, instruction_set: InstructionSet) {
|
||||
self.iwram_bus.invalidate();
|
||||
if instruction_set == InstructionSet::Thumb
|
||||
&& pc >> 24 == 3
|
||||
&& pc.wrapping_add(2) >> 24 == 3
|
||||
{
|
||||
if let (Some(first), Some(second)) = (
|
||||
self.snapshot_mapped_halfword(pc),
|
||||
self.snapshot_mapped_halfword(pc + 2),
|
||||
) {
|
||||
self.iwram_bus.refill(pc, [first, second]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) fn invalidate_cpu_bus_history(&mut self) {
|
||||
self.iwram_bus.invalidate();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
//! Transactional lane history for consecutive Thumb instructions in IWRAM.
|
||||
//! Unknown startup/refill/DMA history is not replaced with current memory bytes.
|
||||
//! Transactional lane history for Thumb IWRAM execution and target-pair refills.
|
||||
//! Unknown startup/DMA history is not replaced with guessed memory bytes.
|
||||
use std::cell::Cell;
|
||||
|
||||
use crate::timing::AccessWidth;
|
||||
|
|
@ -87,6 +87,20 @@ impl IwramBus {
|
|||
}
|
||||
}
|
||||
|
||||
pub(super) fn refill(&mut self, pc: u32, fetched: [u16; 2]) {
|
||||
debug_assert!(self.pending.get().is_none());
|
||||
debug_assert_eq!(pc & 1, 0);
|
||||
let mut lanes = Lanes::default();
|
||||
for (index, half) in fetched.into_iter().enumerate() {
|
||||
lanes.drive(
|
||||
pc + index as u32 * 2,
|
||||
AccessWidth::Halfword,
|
||||
u32::from(half),
|
||||
);
|
||||
}
|
||||
self.committed = Some(History { next_pc: pc, lanes });
|
||||
}
|
||||
|
||||
pub(super) fn invalidate(&mut self) {
|
||||
debug_assert!(self.pending.get().is_none());
|
||||
self.committed = None;
|
||||
|
|
|
|||
|
|
@ -31,7 +31,8 @@ The repository is a Cargo workspace with three crates:
|
|||
| `crates/gba-core/src/cpu/thumb_bios_access_tests.rs` | Thumb BIOS aligned-word snapshots, transitions, load lanes, boundaries, diagnostics, and nominal timing |
|
||||
| `crates/gba-core/src/cpu/thumb_open_bus_tests.rs` | Region-dependent Thumb open bus, mirrors, widths, transfers, source boundaries, isolation, and nominal timing |
|
||||
| `crates/gba-core/src/cpu/iwram_open_bus_tests.rs` | Sequential IWRAM lane history, access widths, isolation, errors, refills, IRQ/DMA invalidation, and nominal timing |
|
||||
| `crates/gba-core/src/memory/iwram_bus.rs` | Transactional known-lane history for sequential Thumb IWRAM execution |
|
||||
| `crates/gba-core/src/cpu/iwram_refill_tests.rs` | Thumb IWRAM target-pair refills, state changes, exception returns, boundaries, isolation, and nominal costs |
|
||||
| `crates/gba-core/src/memory/iwram_bus.rs` | Transactional known-lane history for Thumb IWRAM execution and target-pair refills |
|
||||
| `crates/gba-core/src/cpu/compare_psr_tests.rs` | Original Rd=15 test/compare status restoration, flags, bank, and timing regressions |
|
||||
| `crates/gba-core/src/cpu/status_tests.rs`, `crates/gba-core/src/cpu/exception_tests.rs` | Status, banking, exception, and return tests |
|
||||
| `crates/gba-core/src/cpu/thumb_tests.rs` | Thumb instructions, state switching, and decoder checks |
|
||||
|
|
|
|||
|
|
@ -102,7 +102,7 @@ Limits remain explicit:
|
|||
- Unused/write-only I/O reads, DMA latches, and disabled-RAM reads are not modeled here.
|
||||
- Missing BIOS, truncated ROM, unsupported I/O, and save-memory accesses retain their existing diagnostics.
|
||||
- Unused-memory writes remain diagnostics rather than ignored hardware writes. Swaps cannot silently discard their write.
|
||||
- There is no persistent instruction pipeline. Sequential Thumb IWRAM history does not model refills or DMA-to-CPU bus transitions.
|
||||
- There is no persistent instruction pipeline. Thumb IWRAM refills sample their target pair, but DMA-to-CPU transitions remain unmodeled.
|
||||
|
||||
This subset lets public ARM test 362 complete. That test does not assert the loaded data value.
|
||||
Original regressions check the values separately. See [the public ARM result](../public-arm-tests.md).
|
||||
|
|
@ -162,11 +162,33 @@ Success commits history only for the next sequential Thumb IWRAM PC. Failure pre
|
|||
Block-transfer data accesses stage updates in order; unused-memory reads still use one entry snapshot per instruction.
|
||||
This preserves the existing atomic diagnostic policy without adding bus or device cycles.
|
||||
|
||||
Taken branches and PC-writing refills invalidate continuation history, even when their target is the fallthrough address.
|
||||
Taken branches and PC-writing refills end the old continuation history, even when their target is the fallthrough address.
|
||||
A successful refill into Thumb IWRAM establishes new history from its target pair, as described below.
|
||||
Untaken conditional branches keep sequential history.
|
||||
Other instruction states/regions, accepted machine IRQs, and successful DMA units end the supported history sequence.
|
||||
Failed DMA units leave history unchanged. Discontinuous entry starts unknown instead of borrowing stale lanes.
|
||||
Refill fetches, ARM-to-Thumb history, and DMA latch contents remain unmodeled.
|
||||
Other execution states/regions, accepted machine IRQs, and successful DMA units invalidate continuation history.
|
||||
A later exception return into Thumb IWRAM can establish new history through its refill.
|
||||
Failed DMA units leave history unchanged. Discontinuous entry without an executed refill starts unknown.
|
||||
|
||||
### Thumb IWRAM refill history
|
||||
|
||||
After a successful refill instruction, the emulator uses the resulting PC and instruction state.
|
||||
If the destination is Thumb IWRAM, it samples two halfwords in order: target T, then T+2.
|
||||
Both accesses must remain in IWRAM. Normal physical RAM mirrors apply.
|
||||
These samples establish both word lanes for execution at T. The first instruction then samples T+4 as usual.
|
||||
|
||||
This applies to ARM/Thumb BX, taken Thumb branches, BL suffixes, Thumb PC writes, and ARM status-restoring returns.
|
||||
Saved Thumb state, not the target's low bit alone, controls exception-return sampling.
|
||||
Stack and block-load returns finish their data accesses before the target samples.
|
||||
Failed instructions do not sample a target or replace committed history.
|
||||
|
||||
Snapshots use strict mapped reads and add no nominal data or device cycles.
|
||||
They update bus history only; the interpreter does not cache these instructions for execution.
|
||||
Host inspection does not change captured lanes. A failed target fetch remains a later instruction diagnostic.
|
||||
Cold direct startup, unsupported target states/regions, and region-crossing lookahead still have no inferred refill history.
|
||||
DMA between refill and arrival still invalidates this history rather than supplying a guessed DMA value.
|
||||
|
||||
The [refill evidence and scope](../research/iwram-bus-history.md#thumb-iwram-refill-extension) distinguish these samples from a full pipeline.
|
||||
ARM-target refill history, DMA ordering, self-modifying instruction execution, and exact refill timing remain incomplete.
|
||||
|
||||
## Processor status and exceptions
|
||||
|
||||
|
|
@ -246,7 +268,8 @@ Important timing limits:
|
|||
- Code S/N counts follow instruction summaries, not a simulated fetch pipeline.
|
||||
- Ordinary code costs use the current instruction address. The ARM open-bus PC+8 snapshot has no fetch timing or startup pipeline fill.
|
||||
- PC writes use destination-region costs and the restored instruction width for nominal refill accesses.
|
||||
- Refill cost calculation does not read target bytes. An invalid branch target fails on the following instruction fetch.
|
||||
- Refill cost calculation does not read target bytes. Separate Thumb IWRAM target-pair samples update bus history without extra cycles.
|
||||
- Target-pair sampling cannot fail the branch early. An invalid branch target still fails on the following instruction fetch.
|
||||
- Game Pak prefetch is not implemented. WAITCNT bit 14 is stored but does not accelerate execution.
|
||||
- PHI and SRAM wait fields are stored; PHI output and SRAM mapping are not implemented.
|
||||
- External work RAM timing is fixed. The undocumented memory-control register is not implemented.
|
||||
|
|
|
|||
|
|
@ -50,7 +50,7 @@ Hardware references used for the core:
|
|||
- [NanoBoyAdvance keypad implementation](https://github.com/nba-emu/NanoBoyAdvance/blob/master/src/nba/src/hw/keypad/keypad.cc), compared for control access widths; its AND/retrigger behavior differs from the chosen polling model.
|
||||
- [mGBA keypad timing issue](https://github.com/mgba-emu/mgba/issues/2490), for frontend frame-based input timing limits.
|
||||
- [Tonc hardware interrupts](https://gbadev.net/tonc/interrupts.html), for keypad source enable and IF/IE bit 12.
|
||||
- [GBATEK memory mirrors, video byte writes, and unused-memory reads](https://problemkaputt.de/gbatek-gba-unpredictable-things.htm), for unused address ranges, ARM PC+8 open bus, byte lanes, the distinct Thumb region/history rules, and PC-dependent BIOS read protection. The Thumb implementation follows its 16-bit-region and BIOS/OAM formulas. IWRAM has bounded sequential lane history; refills and region transitions remain unsupported.
|
||||
- [GBATEK memory mirrors, video byte writes, and unused-memory reads](https://problemkaputt.de/gbatek-gba-unpredictable-things.htm), for unused address ranges, ARM PC+8 open bus, byte lanes, the distinct Thumb region/history rules, and PC-dependent BIOS read protection. The Thumb implementation follows its 16-bit-region and BIOS/OAM formulas. IWRAM has bounded sequential lane history and Thumb target-pair refill samples; region transitions remain unsupported.
|
||||
- [nocash GBA open-bus discussion](https://www.ngemu.com/threads/gba-open-bus.170809/), for ARM prefetch, repeated Thumb halfwords in 16-bit regions, aligned BIOS/OAM words, and history-dependent IWRAM lanes. Its data-load overwrite note prevents treating P+2 as a universal IWRAM rule.
|
||||
- [mGBA memory implementation](https://github.com/mgba-emu/mgba/blob/master/src/gba/memory.c), reviewed for `GBALoadBad`, ARM prefetch sourcing, byte/halfword lane selection, and separate DMA/history behavior. Also reviewed its BIOS region-exit prefetch retention and protected-load lane selection.
|
||||
- [GBATEK GBA memory map and bus widths](https://problemkaputt.de/gbatek-gba-memory-map.htm).
|
||||
|
|
@ -112,6 +112,15 @@ IWRAM lane-history research:
|
|||
|
||||
See [IWRAM Thumb bus history](research/iwram-bus-history.md). These were source reviews, not local hardware or external-emulator test runs.
|
||||
|
||||
IWRAM refill research:
|
||||
|
||||
- [ARM7TDMI branch cycle sequence](https://support.arm.com/documentation/ddi0029/g/instruction-cycle-timings/branch-and-branch-with-link), for destination and destination+instruction-width fetches.
|
||||
- [ARM7TDMI Thumb BL sequence](https://support.arm.com/documentation/ddi0210/c/Instruction-Cycle-Timings/Thumb-branch-with-link), for the prefix/suffix distinction.
|
||||
- [ARM7TDMI load-multiple sequence](https://support.arm.com/documentation/ddi0029/g/instruction-cycle-timings/load-multiple-registers), for data-transfer ordering before PC-load refills.
|
||||
- [NanoBoyAdvance refill helpers](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/arm/arm7tdmi.hh), reviewed for Thumb target/target+2 fetch order and the following execution fetch.
|
||||
|
||||
These sources support bounded refill sampling, not a claim of cycle-accurate pipeline or DMA behavior.
|
||||
|
||||
Use [GBATEK](https://problemkaputt.de/gbatek.htm) and ARM7TDMI documentation for further hardware work.
|
||||
Only use game ROMs that you may lawfully use. Do not commit game ROMs, BIOS files, or game assets.
|
||||
The ignore file excludes `roms/`, common game ROM extensions, and save files.
|
||||
|
|
|
|||
|
|
@ -48,15 +48,43 @@ Ordinary instructions and mapped data accesses can establish history without req
|
|||
Consecutive halfword fetches or an IWRAM word access can make every lane known.
|
||||
Missing lookahead and 16 MiB region-crossing fetches retain diagnostics.
|
||||
|
||||
Successful branches and other refill instructions invalidate continuation history, even when the target equals the next sequential address.
|
||||
The existing Thumb timing classifier identifies these refills for both timed and untimed CPU stepping.
|
||||
Execution outside Thumb IWRAM also ends this bounded history sequence.
|
||||
An accepted machine IRQ and each successful DMA unit invalidate the history. Failed DMA units preserve it.
|
||||
The implementation does not guess refill or DMA latch contents.
|
||||
The initial sequential-only implementation invalidated history after all refill instructions.
|
||||
The extension below now establishes target-pair history for successful refills into Thumb IWRAM.
|
||||
The existing ARM/Thumb timing classifiers identify these refills for both timed and untimed CPU stepping.
|
||||
Execution outside Thumb IWRAM still ends a sequential history sequence.
|
||||
An accepted machine IRQ and each successful DMA unit invalidate history. Failed DMA units preserve it.
|
||||
The implementation does not guess DMA latch contents.
|
||||
|
||||
This is not a full IWRAM bus model across all CPU states. ARM access history, refill fetches, and DMA-to-CPU ordering remain incomplete.
|
||||
This is not a full IWRAM bus model across all CPU states. ARM-target history and DMA-to-CPU ordering remain incomplete.
|
||||
It is not a persistent instruction pipeline. Self-modifying instruction execution and exact per-access device timing remain unverified.
|
||||
|
||||
## Thumb IWRAM refill extension
|
||||
|
||||
The [ARM7TDMI branch sequence](https://support.arm.com/documentation/ddi0029/g/instruction-cycle-timings/branch-and-branch-with-link) fetches the destination, then destination plus instruction width.
|
||||
For Thumb destinations, those addresses are T and T+2.
|
||||
[NanoBoyAdvance's refill helpers](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/arm/arm7tdmi.hh) use that order.
|
||||
Its execution loop then fetches T+4 before executing the first Thumb instruction.
|
||||
|
||||
After a successful refill instruction, we sample the two mapped destination halfwords if both remain in Thumb IWRAM.
|
||||
The samples replace the old lane history and establish the next expected PC as T.
|
||||
The next instruction's normal PC+4 sample updates one lane while the other retains the captured T+2 halfword.
|
||||
The samples occur after data accesses and status restoration, so loaded PC values and saved Thumb state select the destination.
|
||||
|
||||
This covers actual ARM/Thumb BX, taken Thumb branches, BL suffixes, PC-writing Thumb operations, and ARM status-restoring returns.
|
||||
The Thumb BL prefix alone does not refill.
|
||||
Failed instructions retain the previous committed history. An unsupported or incomplete target sample does not fail the branch early.
|
||||
Unmapped instruction targets still fail on the following fetch.
|
||||
Cold direct startup and arbitrary PC changes do not manufacture a refill.
|
||||
|
||||
These are bus-history samples, not instruction-buffer contents or extra emulated cycles.
|
||||
The interpreter still reads instructions when it executes them.
|
||||
Changing T+2 after the branch does not replace its captured bus value; changing T+4 before arrival affects the later sample.
|
||||
Those original tests verify sample ordering, not hardware-accurate self-modifying instruction execution.
|
||||
|
||||
Successful DMA still invalidates history, including between refill and arrival.
|
||||
ARM-target refill history, exact pipeline timing, and DMA-to-CPU ordering remain outside this extension.
|
||||
No external emulator differential run or physical-hardware test was performed.
|
||||
|
||||
## Original regression coverage
|
||||
|
||||
- Both code alignments, IWRAM mirrors, and physical RAM wrap.
|
||||
|
|
@ -66,11 +94,14 @@ It is not a persistent instruction pipeline. Self-modifying instruction executio
|
|||
- Multiple-register transfers, final-word retention, and writeback.
|
||||
- Unknown lanes, establishment of known history, staged-access rollback, and retry.
|
||||
- Taken and untaken branches, PC writes to fallthrough, discontinuities, IRQ entry, and DMA success/failure.
|
||||
- ARM/Thumb source regions, both target alignments, refill sample ordering, stack/block returns, and saved User/System banks.
|
||||
- Actual SWI/IRQ return handlers, failed refills, unmapped targets, separate BIOS history, and DMA between refill and arrival.
|
||||
- Equal timed/untimed CPU results and unchanged nominal data/device costs.
|
||||
|
||||
## Validation result
|
||||
|
||||
The sequential-history regressions reproduced the old unsupported-read failures before implementation.
|
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The refill regressions also failed on the prior invalidation-only path, then passed with target-pair sampling.
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Workspace and core/demo tests pass on Darwin arm64 in debug and release builds.
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Formatting, lint checks, rustdoc, preparation tests, native ROM windows, and graphics smoke modes also pass.
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Public ARM, Thumb, memory, and BIOS reports match their previous passing results exactly.
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@ -74,6 +74,7 @@ Update this file when a feature lands or a limit is removed.
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- ARM unused-memory data reads return a PC+8 word snapshot, with normal byte lanes and load rotation.
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||||
- Thumb unused-memory reads use repeated PC+4 halfwords in 16-bit code regions and aligned PC+4 words in BIOS/OAM.
|
||||
- Sequential Thumb IWRAM history retains fetched and data-access lanes, with known-bit tracking and diagnostic rollback.
|
||||
- Successful refills into Thumb IWRAM establish bus history from the target and target+2 halfwords, including exception returns.
|
||||
- Little-endian byte, halfword, and word reads/writes.
|
||||
- ARM7TDMI word-load rotation, aligned stores, and odd-address halfword-load behavior.
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||||
- Explicit errors for unsupported instructions when their condition passes, and for unsupported memory accesses.
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||||
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|
@ -134,8 +135,9 @@ The runner requires known completion addresses and has no debug-port protocol, s
|
|||
ARM data reads from unused address ranges use a bounded [PC+8 open-bus snapshot](hardware/cpu.md#arm-unused-memory-data-reads).
|
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Thumb reads use [region-dependent snapshots](hardware/cpu.md#thumb-unused-memory-data-reads) and bounded sequential IWRAM lane history.
|
||||
Cold or invalidated IWRAM history remains diagnostic until all lanes are known.
|
||||
Refill instructions, accepted machine IRQs, successful DMA, and execution outside Thumb IWRAM end the supported history sequence.
|
||||
This is not a fetch pipeline. Refill history, region-crossing fetches, DMA latches, and unused/write-only I/O open bus remain unsupported.
|
||||
Refills into Thumb IWRAM establish new target-pair history after the instruction succeeds.
|
||||
Accepted machine IRQs, successful DMA, unsupported refills, and other execution states/regions invalidate continuation history.
|
||||
This is not a fetch pipeline. ARM-target refill history, region-crossing fetches, DMA latches, and unused/write-only I/O open bus remain unsupported.
|
||||
BIOS protection uses separate retained BIOS fetch snapshots as described in [BIOS behavior](hardware/bios.md#cpu-bios-read-protection).
|
||||
Host inspection and instruction fetches remain strict. Other unmapped reads return errors.
|
||||
Reads beyond the supplied cartridge bytes also return errors.
|
||||
|
|
@ -145,7 +147,7 @@ Writes to cartridge addresses return errors instead of modeling cartridge hardwa
|
|||
|
||||
## Next steps
|
||||
|
||||
1. Extend IWRAM history across validated refill and DMA-to-CPU transitions.
|
||||
1. Research and validate DMA-to-CPU bus history, including latch ownership and IWRAM effects.
|
||||
Keep unknown history diagnostic until fetch ordering and latch ownership have independent coverage.
|
||||
Validate BIOS snapshots with independent hardware tests before claiming exact refill or data-access history.
|
||||
The desktop runner still uses only the original BIOS. Keep protected reads image-derived for all supplied images.
|
||||
|
|
|
|||
|
|
@ -72,7 +72,10 @@ Short-ROM tests require only the fetched halfword in 16-bit regions. Cold IWRAM
|
|||
Sequential IWRAM regressions check retained lanes across fetches, reads, writes, mirrors, and physical RAM wrap.
|
||||
They cover raw bus values before load rotation/sign extension, all modes, block transfers, and isolation from other memory regions.
|
||||
Known-bit tests reject incomplete words. Transaction tests verify discarded partial updates and preserved history after errors.
|
||||
Control-flow tests distinguish taken/untaken branches and invalidate PC writes even when the target equals fallthrough.
|
||||
Control-flow tests distinguish taken/untaken branches and refill Thumb IWRAM targets even when the target equals fallthrough.
|
||||
Refill tests cover ARM/Thumb BX, Thumb branches and BL, high-register PC writes, stack/block PC loads, and saved-state returns.
|
||||
They check both target alignments, mirrors/wrap, captured target+2 versus later target+4, widths, sign extension, and rotation.
|
||||
Original SWI/IRQ handlers verify return-time history. Failed returns, cold entry, region boundaries, DMA invalidation, and BIOS isolation retain checks.
|
||||
DMA and IRQ tests check conservative invalidation; timed/untimed tests verify CPU results and nominal clock costs.
|
||||
Host/fetch isolation, separate BIOS history, unsupported stores/data regions, nominal device progression, and DMA diagnostics also have checks.
|
||||
The pinned public ARM ROM now reaches its completion checkpoint with r12 = 0 in debug and release builds.
|
||||
|
|
@ -233,7 +236,7 @@ They cover all processor modes, load widths, lanes, rotation, both Thumb code al
|
|||
They verify direct reads while executing inside BIOS, re-entry, SWI/IRQ returns, host-inspection isolation, and original-boot provenance.
|
||||
Thumb tests cover sequential snapshots, instruction-state transitions, SWI entry, and RAM-backed POP exits.
|
||||
Unknown history, last valid fetch words, missing lookahead, and diagnostic-step retention have explicit checks.
|
||||
Unknown Thumb IWRAM history remains diagnostic. Separate tests cover known sequential history, general Thumb snapshots, and retained BIOS history.
|
||||
Unknown Thumb IWRAM history remains diagnostic. Separate tests cover sequential/refill history, general Thumb snapshots, and retained BIOS history.
|
||||
Protected loads keep normal nominal costs and advance devices only through machine stepping.
|
||||
Firmware readback regressions separately verify documented boot, SoftReset, returning SWI, IRQ callback, and IRQ return words.
|
||||
They execute ARM/Thumb loads across widths and lanes, check caller state, and trace actual exits to their image data.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue