feat(memory): sample Thumb IWRAM refill targets
After successful refill instructions, sample the Thumb IWRAM target and target+2 halfwords to establish bus history. Share ARM/Thumb refill classification with nominal timing. Respect restored instruction state, completed data accesses, region limits, and diagnostic rollback; keep instruction execution and nominal costs unchanged. Add original regressions for ARM/Thumb BX, Thumb branches and BL, PC writes, stack/block PC loads, status-restoring returns, real SWI/IRQ returns, both target alignments, mirrors/wrap, captured sample ordering, load lanes, failure retention, BIOS isolation, and DMA invalidation. Document official ARM7TDMI refill evidence and the distinction from a full pipeline. Darwin arm64 validation: 917 workspace tests and 848 core/demo tests per debug/release profile; 39 preparation tests; native ROM windows in both profiles; ten graphics/window smoke modes; fmt, clippy, and rustdoc. Public ARM, Thumb, memory, and BIOS reports remain identical to prior passing results and between profiles. Cold startup, ARM-target refill history, and DMA-to-CPU ordering remain incomplete; no hardware-conformance or commercial-game claim.
This commit is contained in:
0xrsydn
parent
46af481487
commit
8b0f1a5ead
12 changed files with 566 additions and 35 deletions
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@ -24,6 +24,8 @@ mod instruction_tests;
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#[cfg(test)]
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mod iwram_open_bus_tests;
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#[cfg(test)]
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mod iwram_refill_tests;
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#[cfg(test)]
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mod load_alias_tests;
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#[cfg(test)]
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mod open_bus_tests;
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@ -211,14 +213,17 @@ impl Cpu {
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// Record the executing instruction, not an operand's pipelined PC value.
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// Always clear the access context, including on diagnostic errors.
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let pc = self.pc();
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let sequential_thumb =
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self.instruction_set == InstructionSet::Thumb && !self.thumb_refills(instruction);
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let refill = self.instruction_refills(instruction);
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let sequential_thumb = self.instruction_set == InstructionSet::Thumb && !refill;
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memory.begin_cpu_access(pc, self.instruction_set);
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let result = self.execute_instruction(instruction, memory);
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let sequential = sequential_thumb
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&& self.instruction_set == InstructionSet::Thumb
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&& self.pc() == pc.wrapping_add(2);
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memory.end_cpu_access(result.is_ok(), sequential);
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if result.is_ok() && refill {
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memory.refill_cpu_bus_history(self.pc(), self.instruction_set);
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}
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result
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}
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@ -295,7 +295,7 @@ fn failed_steps_discard_prefetch_history_before_retry() {
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}
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#[test]
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fn taken_control_flow_invalidates_history_even_when_target_is_fallthrough() {
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fn taken_control_flow_refills_history_even_when_target_is_fallthrough() {
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for branch in [0x4720, 0xe7ff, 0x46a7, 0xd0ff, 0xbd00] {
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// BX, B, MOV pc, BEQ, POP pc.
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let (mut cpu, mut bus) = program(CODE, &[SEED, branch, PROBE, 0x5566, 0x99aa]);
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@ -306,12 +306,8 @@ fn taken_control_flow_invalidates_history_even_when_target_is_fallthrough() {
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cpu.step(&mut bus).unwrap();
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), CODE + 4);
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let before = cpu.clone();
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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assert_eq!(cpu, before);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], 0x5566_99aa);
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}
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let (mut cpu, mut bus) = program(CODE, &[SEED, 0xd0ff, PROBE, 0x5566, 0x99aa]);
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cpu.flags.zero = false; // Untaken BEQ has no refill.
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425
crates/gba-core/src/cpu/iwram_refill_tests.rs
Normal file
425
crates/gba-core/src/cpu/iwram_refill_tests.rs
Normal file
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@ -0,0 +1,425 @@
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//! Original control-flow programs for Thumb IWRAM refill-lane snapshots.
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use super::*;
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use crate::{
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dma::{DMA_BASE, DMA_STRIDE},
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io::{IE, IME, TIMER_BASE},
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machine::{Machine, MachineError, StepKind},
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memory::{BIOS_SIZE, ROM_START},
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};
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const SOURCE: u32 = 0x0300_0100;
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const TARGET: u32 = 0x0300_0200;
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const STACK: u32 = 0x0300_1000;
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const UNUSED: u32 = 0x8000_0000;
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const PROBE: u16 = 0x6806; // LDR r6,[r0]
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const MARKER: u16 = 0x91ab;
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const LOOKAHEAD: u16 = 0xd234;
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fn target(bus: &mut Memory, pc: u32, instruction: u16) {
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for (index, half) in [instruction, MARKER, LOOKAHEAD, 0x5678]
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.into_iter()
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.enumerate()
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{
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bus.write16(pc + index as u32 * 2, half).unwrap();
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}
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}
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fn expected(pc: u32) -> u32 {
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if pc & 2 == 0 {
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0x91ab_d234
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} else {
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0xd234_91ab
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}
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}
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fn branch(source: u32, thumb: bool, destination: u32) -> (Cpu, Memory) {
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let instruction: u32 = if thumb { 0x46c0_4720 } else { 0xe12f_ff14 }; // BX r4
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let mut bus = if source < BIOS_SIZE as u32 {
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let mut bios = vec![0; BIOS_SIZE];
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bios[source as usize..source as usize + 4].copy_from_slice(&instruction.to_le_bytes());
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Memory::with_bios(vec![], bios).unwrap()
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} else if source == ROM_START {
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Memory::new(instruction.to_le_bytes().to_vec()).unwrap()
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} else {
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let mut bus = Memory::new(vec![]).unwrap();
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bus.write32(source, instruction).unwrap();
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bus
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};
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target(&mut bus, destination, PROBE);
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let mut cpu = Cpu::new(source);
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cpu.instruction_set = if thumb {
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InstructionSet::Thumb
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} else {
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InstructionSet::Arm
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};
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cpu.registers[0] = UNUSED;
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cpu.registers[4] = destination | 1;
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(cpu, bus)
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}
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#[test]
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fn arm_and_thumb_bx_establish_history_at_both_target_alignments_and_mirrors() {
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for source in [0x100, 0x0200_0100, SOURCE, ROM_START] {
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for thumb in [false, true] {
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for destination in [
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TARGET,
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TARGET + 2,
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TARGET + 0x8000,
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0x0300_7ffc,
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0x0300_7ffe,
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] {
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let (mut cpu, mut bus) = branch(source, thumb, destination);
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let status = cpu.cpsr() | 0xb000_00c0;
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cpu.apply_status(status, Mode::System);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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assert_eq!(cpu.instruction_set(), InstructionSet::Thumb);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], expected(destination));
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assert_eq!(cpu.cpsr(), status | 0x20);
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assert_eq!(cpu.registers[4], destination | 1);
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}
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}
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}
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}
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#[test]
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fn refill_samples_target_plus_two_at_branch_time_but_plus_four_on_arrival() {
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for destination in [TARGET, TARGET + 2] {
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let (mut cpu, mut bus) = branch(ROM_START, false, destination);
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cpu.step(&mut bus).unwrap();
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bus.write16(destination + 2, 0xeeee).unwrap();
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bus.write16(destination + 4, 0xabcd).unwrap();
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assert_eq!(bus.read16(destination + 2).unwrap(), 0xeeee);
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cpu.step(&mut bus).unwrap();
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assert_eq!(
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cpu.registers[6],
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if destination & 2 == 0 {
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0x91ab_abcd
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} else {
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0xabcd_91ab
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}
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);
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}
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}
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#[test]
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fn refill_history_supports_normal_load_lanes_rotation_and_sign_extension() {
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for destination in [TARGET, TARGET + 2] {
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let word = expected(destination);
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for (instruction, width, signed) in [
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(PROBE, 4, false),
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(0x7806, 1, false),
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(0x8806, 2, false),
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(0x5746, 1, true),
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(0x5f46, 2, true), // r5=0 offset, r6 result.
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] {
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for lane in 0..4 {
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let (mut cpu, mut bus) = branch(ROM_START, false, destination);
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target(&mut bus, destination, instruction);
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cpu.registers[0] += lane;
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cpu.step(&mut bus).unwrap();
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let byte = (word >> (lane * 8)) as u8;
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let half = (word >> ((lane & 2) * 8)) as u16;
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let value = match (width, signed) {
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(4, _) => word.rotate_right(lane * 8),
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(1, false) => u32::from(byte),
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(1, true) => byte as i8 as i32 as u32,
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(2, false) => u32::from(half).rotate_right((lane & 1) * 8),
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(2, true) if lane & 1 != 0 => byte as i8 as i32 as u32,
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(2, true) => half as i16 as i32 as u32,
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_ => unreachable!(),
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};
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let mut after = cpu.clone();
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after.registers[6] = value;
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after.registers[15] += 2;
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu, after);
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}
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}
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}
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}
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#[test]
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fn thumb_pc_writes_refill_after_data_loads_and_preserve_transfer_semantics() {
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for destination in [TARGET, TARGET + 2] {
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for instruction in [0x4720, 0x46a7, 0x44a7, 0xbd00, 0xbc00, 0xcc00] {
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// BX r4, MOV pc,r4, ADD pc,r4, POP {pc}, empty POP, empty LDM r4!.
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let (mut cpu, mut bus) = branch(SOURCE, true, destination);
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bus.write16(SOURCE, instruction).unwrap();
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bus.write32(STACK, destination).unwrap();
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cpu.registers[13] = STACK;
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cpu.registers[4] = match instruction {
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0xcc00 => STACK,
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0x44a7 => destination.wrapping_sub(SOURCE + 4),
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_ => destination | 1,
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};
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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assert_eq!(cpu.instruction_set(), InstructionSet::Thumb);
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if instruction == 0xbd00 {
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assert_eq!(cpu.registers[13], STACK + 4);
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}
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if instruction == 0xbc00 {
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assert_eq!(cpu.registers[13], STACK + 64);
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}
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if instruction == 0xcc00 {
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assert_eq!(cpu.registers[4], STACK + 64);
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(
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cpu.registers[6],
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expected(destination),
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"instruction={instruction:#x}"
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);
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}
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}
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}
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#[test]
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fn thumb_taken_branches_and_bl_suffix_establish_target_history() {
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for destination in [TARGET, TARGET + 2] {
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for kind in 0..3 {
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let (mut cpu, mut bus) = branch(SOURCE, true, destination);
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if kind == 2 {
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bus.write16(SOURCE, 0xf000).unwrap(); // BL prefix: high offset zero.
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bus.write16(SOURCE + 2, 0xf800 | ((destination - SOURCE - 4) / 2) as u16)
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.unwrap();
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), SOURCE + 2);
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} else {
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let offset = ((destination - SOURCE - 4) / 2) as u16;
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bus.write16(
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SOURCE,
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if kind == 0 {
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0xe000 | offset
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} else {
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0xd000 | offset
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},
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)
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.unwrap();
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cpu.flags.zero = true;
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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if kind == 2 {
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assert_eq!(cpu.registers[14], (SOURCE + 4) | 1);
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], expected(destination));
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}
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}
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}
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#[test]
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fn arm_exception_returns_use_saved_thumb_state_and_restored_banks() {
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for destination in [TARGET, TARGET + 2] {
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for mode in [Mode::User, Mode::System] {
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for instruction in [0xe1b0_f00e_u32, 0xe25e_f004, 0xe8fd_8004] {
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// MOVS pc,lr; SUBS pc,lr,#4; LDMIA sp!,{r2,pc}^.
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let mut bus = Memory::new(instruction.to_le_bytes().to_vec()).unwrap();
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target(&mut bus, destination, PROBE);
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bus.write32(STACK, 0xfeed_beef).unwrap();
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bus.write32(STACK + 4, destination).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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cpu.registers[13] = 0x0300_7000;
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cpu.registers[14] = 0x1234;
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cpu.enter_exception(Exception::SoftwareInterrupt);
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cpu.registers[15] = ROM_START;
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cpu.registers[13] = STACK;
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cpu.registers[14] = destination + if instruction == 0xe25e_f004 { 4 } else { 0 };
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let status = 0xa000_00e0 | mode as u32;
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cpu.set_spsr(status);
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.pc(), destination);
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assert_eq!(cpu.cpsr(), status);
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assert_eq!(cpu.registers[13], 0x0300_7000);
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assert_eq!(cpu.registers[14], 0x1234);
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if instruction == 0xe8fd_8004 {
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assert_eq!(cpu.registers[2], 0xfeed_beef);
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}
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], expected(destination));
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cpu.switch_mode(Mode::Supervisor);
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assert_eq!(
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cpu.registers[13],
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STACK + if instruction == 0xe8fd_8004 { 8 } else { 0 }
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);
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}
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}
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}
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}
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#[test]
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fn real_swi_and_irq_returns_can_resume_thumb_iwram_with_known_lanes() {
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for irq in [false, true] {
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let destination = if irq { TARGET } else { TARGET + 2 };
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let mut bios = vec![0; BIOS_SIZE];
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bios[8..12].copy_from_slice(&0xe1b0_f00e_u32.to_le_bytes());
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bios[0x18..0x1c].copy_from_slice(&0xe25e_f004_u32.to_le_bytes());
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let mut bus = Memory::with_bios(vec![], bios).unwrap();
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target(&mut bus, destination, PROBE);
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if !irq {
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bus.write16(TARGET, 0xdf00).unwrap();
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}
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let mut cpu = Cpu::new(TARGET);
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cpu.instruction_set = InstructionSet::Thumb;
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cpu.registers[0] = UNUSED;
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let status = cpu.cpsr();
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let mut machine = Machine::new(cpu, bus);
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if irq {
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machine.memory_mut().write16(IE, 8).unwrap();
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machine.memory_mut().write16(IME, 1).unwrap();
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machine
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.memory_mut()
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.write32(TIMER_BASE, 0x00c0_ffff)
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.unwrap();
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machine.memory_mut().advance_cycles(1);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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machine.memory_mut().write16(IME, 0).unwrap(); // Keep this test to one IRQ entry.
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} else {
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machine.step().unwrap();
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}
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machine.step().unwrap(); // Execute the original ARM return handler.
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assert_eq!(machine.cpu().pc(), destination);
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assert_eq!(machine.cpu().cpsr(), status);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[6], expected(destination));
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}
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}
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#[test]
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fn failed_refill_instructions_preserve_cpu_and_preexisting_history() {
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for instruction in [0xe1b0_f00e_u32, 0xe8fd_8004] {
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let mut bus = Memory::new(instruction.to_le_bytes().to_vec()).unwrap();
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for (index, half) in [0x680a_u16, PROBE, 0x1111, LOOKAHEAD]
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.into_iter()
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.enumerate()
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{
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bus.write16(SOURCE + index as u32 * 2, half).unwrap();
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}
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bus.write32(STACK, 0x1234_abcd).unwrap();
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let mut paused = Cpu::new(SOURCE);
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paused.instruction_set = InstructionSet::Thumb;
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paused.registers[0] = UNUSED;
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paused.registers[1] = STACK;
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paused.step(&mut bus).unwrap(); // Seed sequential history with a word load.
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let mut failing = Cpu::at_reset();
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failing.registers[15] = ROM_START;
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failing.registers[13] = STACK;
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failing.registers[14] = TARGET;
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failing.set_spsr(0); // Invalid return mode; no refill must commit.
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let before = failing.clone();
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assert!(failing.step_timed(&mut bus).is_err());
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assert_eq!(failing, before);
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paused.step(&mut bus).unwrap();
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assert_eq!(paused.registers[6], 0xd234_abcd);
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}
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}
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#[test]
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fn cold_entry_region_crossings_and_unmapped_targets_do_not_invent_refill_history() {
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let mut bus = Memory::new(vec![]).unwrap();
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target(&mut bus, TARGET, PROBE);
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let mut cpu = Cpu::new(TARGET);
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cpu.instruction_set = InstructionSet::Thumb;
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cpu.registers[0] = UNUSED;
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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for destination in [0x03ff_fffc, 0x03ff_fffe, 0x0e00_0000] {
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let mut bus = Memory::new(0xe12f_ff14_u32.to_le_bytes().to_vec()).unwrap();
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if destination >> 24 == 3 {
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bus.write16(destination, PROBE).unwrap();
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}
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let mut cpu = Cpu::new(ROM_START);
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cpu.registers[0] = UNUSED;
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cpu.registers[4] = destination | 1;
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cpu.step(&mut bus).unwrap(); // An unavailable target/refill never fails BX early.
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assert_eq!(cpu.pc(), destination);
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let before = cpu.clone();
|
||||
assert_eq!(
|
||||
cpu.step(&mut bus),
|
||||
Err(CpuError::Memory(MemoryError::Unmapped(
|
||||
if destination >> 24 == 3 {
|
||||
UNUSED
|
||||
} else {
|
||||
destination
|
||||
}
|
||||
)))
|
||||
);
|
||||
assert_eq!(cpu, before);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn target_pair_refill_does_not_replace_the_separate_bios_retained_word() {
|
||||
for destination in [TARGET, TARGET + 2] {
|
||||
let mut bios = vec![0; BIOS_SIZE];
|
||||
bios[0x100..0x104].copy_from_slice(&0xe12f_ff14_u32.to_le_bytes());
|
||||
bios[0x108..0x10c].copy_from_slice(&0x89ab_cdef_u32.to_le_bytes());
|
||||
let mut bus = Memory::with_bios(vec![], bios).unwrap();
|
||||
target(&mut bus, destination, PROBE);
|
||||
let mut cpu = Cpu::new(0x100);
|
||||
cpu.registers[4] = destination | 1;
|
||||
cpu.step(&mut bus).unwrap();
|
||||
cpu.step(&mut bus).unwrap(); // r0=0: protected BIOS read, not unused memory.
|
||||
assert_eq!(cpu.registers[6], 0x89ab_cdef);
|
||||
assert_eq!(bus.read32(0x108).unwrap(), 0x89ab_cdef);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn successful_dma_between_refill_and_target_execution_invalidates_refill_history() {
|
||||
let (cpu, mut bus) = branch(ROM_START, false, TARGET);
|
||||
bus.write32(STACK, 0x1234_abcd).unwrap();
|
||||
let mut machine = Machine::new(cpu, bus);
|
||||
machine.step().unwrap();
|
||||
let dma = DMA_BASE + 3 * DMA_STRIDE;
|
||||
machine.memory_mut().write32(dma, STACK).unwrap();
|
||||
machine.memory_mut().write32(dma + 4, 0x0200_0000).unwrap();
|
||||
machine.memory_mut().write32(dma + 8, 0x8400_0001).unwrap();
|
||||
assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 3 });
|
||||
let before = machine.cpu().clone();
|
||||
let timing = machine.last_timing();
|
||||
let cycles = machine.cycles();
|
||||
assert_eq!(
|
||||
machine.step(),
|
||||
Err(MachineError::Cpu(CpuError::Memory(MemoryError::Unmapped(
|
||||
UNUSED
|
||||
))))
|
||||
);
|
||||
assert_eq!(machine.cpu(), &before);
|
||||
assert_eq!(machine.last_timing(), timing);
|
||||
assert_eq!(machine.cycles(), cycles);
|
||||
assert_eq!(machine.cpu().pc(), TARGET);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn refill_snapshots_keep_existing_nominal_costs_and_timed_untimed_results() {
|
||||
for thumb in [false, true] {
|
||||
for destination in [TARGET, TARGET + 2] {
|
||||
let (cpu, mut bus) = branch(ROM_START, thumb, destination);
|
||||
bus.write32(TIMER_BASE, 0x0080_0000).unwrap();
|
||||
let mut machine = Machine::new(cpu, bus);
|
||||
let (mut untimed, mut bus) = branch(ROM_START, thumb, destination);
|
||||
for index in 0..2 {
|
||||
untimed.step(&mut bus).unwrap();
|
||||
machine.step().unwrap();
|
||||
assert_eq!(machine.cpu(), &untimed);
|
||||
assert_eq!(
|
||||
machine.last_timing().code_cycles,
|
||||
if index == 0 { 3 } else { 1 }
|
||||
);
|
||||
assert_eq!(machine.last_timing().data_cycles, index);
|
||||
assert_eq!(machine.last_timing().internal_cycles, index);
|
||||
}
|
||||
assert_eq!(machine.cycles(), 6);
|
||||
assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 6);
|
||||
assert_eq!(bus.cycles(), 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
//! Nominal ARM7 instruction-cycle summaries, separate from instruction semantics.
|
||||
//! Data costs come from actual bus accesses. No speculative pipeline reads occur.
|
||||
//! Data costs come from actual bus accesses. Bus-history samples are separate from timing calculations.
|
||||
//! PC writes use target-region code costs, following GBATEK's cycle summary.
|
||||
|
||||
use super::{Cpu, CpuError, InstructionSet};
|
||||
|
|
@ -151,8 +151,11 @@ impl Cpu {
|
|||
|
||||
// Share the existing control-flow classification with bounded bus history.
|
||||
// A PC write can refill even when its target equals the sequential address.
|
||||
pub(super) fn thumb_refills(&self, instruction: u32) -> bool {
|
||||
self.thumb_summary(instruction).refill
|
||||
pub(super) fn instruction_refills(&self, instruction: u32) -> bool {
|
||||
match self.instruction_set {
|
||||
InstructionSet::Arm => self.arm_summary(instruction).refill,
|
||||
InstructionSet::Thumb => self.thumb_summary(instruction).refill,
|
||||
}
|
||||
}
|
||||
|
||||
fn thumb_summary(&self, instruction: u32) -> Summary {
|
||||
|
|
|
|||
|
|
@ -66,7 +66,8 @@ struct CpuAccess {
|
|||
/// Unused-memory reads use ARM PC+8 or supported region-dependent Thumb snapshots.
|
||||
/// Protected BIOS reads separately retain the snapshot from BIOS execution.
|
||||
/// Sequential Thumb IWRAM accesses retain addressed bus lanes transactionally.
|
||||
/// Refill history, a full fetch pipeline, and DMA bus latches are not modeled.
|
||||
/// Successful refills into Thumb IWRAM sample the target pair to establish history.
|
||||
/// A full fetch pipeline, ARM-target refill history, and DMA bus latches are not modeled.
|
||||
pub struct Memory {
|
||||
external_ram: Vec<u8>,
|
||||
internal_ram: Vec<u8>,
|
||||
|
|
@ -400,6 +401,24 @@ impl Memory {
|
|||
}
|
||||
}
|
||||
|
||||
/// Sample only the two target fetches of a completed refill into Thumb IWRAM.
|
||||
/// This updates bus history, not the CPU's instruction buffer or nominal costs.
|
||||
/// Incomplete or unsupported refills stay unknown without failing the branch early.
|
||||
pub(crate) fn refill_cpu_bus_history(&mut self, pc: u32, instruction_set: InstructionSet) {
|
||||
self.iwram_bus.invalidate();
|
||||
if instruction_set == InstructionSet::Thumb
|
||||
&& pc >> 24 == 3
|
||||
&& pc.wrapping_add(2) >> 24 == 3
|
||||
{
|
||||
if let (Some(first), Some(second)) = (
|
||||
self.snapshot_mapped_halfword(pc),
|
||||
self.snapshot_mapped_halfword(pc + 2),
|
||||
) {
|
||||
self.iwram_bus.refill(pc, [first, second]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) fn invalidate_cpu_bus_history(&mut self) {
|
||||
self.iwram_bus.invalidate();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
//! Transactional lane history for consecutive Thumb instructions in IWRAM.
|
||||
//! Unknown startup/refill/DMA history is not replaced with current memory bytes.
|
||||
//! Transactional lane history for Thumb IWRAM execution and target-pair refills.
|
||||
//! Unknown startup/DMA history is not replaced with guessed memory bytes.
|
||||
use std::cell::Cell;
|
||||
|
||||
use crate::timing::AccessWidth;
|
||||
|
|
@ -87,6 +87,20 @@ impl IwramBus {
|
|||
}
|
||||
}
|
||||
|
||||
pub(super) fn refill(&mut self, pc: u32, fetched: [u16; 2]) {
|
||||
debug_assert!(self.pending.get().is_none());
|
||||
debug_assert_eq!(pc & 1, 0);
|
||||
let mut lanes = Lanes::default();
|
||||
for (index, half) in fetched.into_iter().enumerate() {
|
||||
lanes.drive(
|
||||
pc + index as u32 * 2,
|
||||
AccessWidth::Halfword,
|
||||
u32::from(half),
|
||||
);
|
||||
}
|
||||
self.committed = Some(History { next_pc: pc, lanes });
|
||||
}
|
||||
|
||||
pub(super) fn invalidate(&mut self) {
|
||||
debug_assert!(self.pending.get().is_none());
|
||||
self.committed = None;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue