0xrsydn/gameboy-rust
1
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

refactor(cpu): account for timing in bus-access order

Browse source
This commit is contained in:
0xrsydn 2026-10-06 17:16:08 +07:00
commit 7f3ebd3a5d
14 changed files with 626 additions and 65 deletions
Download patch file Download diff file Expand all files Collapse all files

3
docs/research/fetch-access-sequencing.md
View file

@ -126,4 +126,5 @@ The timer therefore runs two additional cycles before the handler stops it.
- Game Pak prefetch, configurable EWRAM timing, display contention, and DMA during internal cycles remain unimplemented.
- IRQ synchronization delays and complete BIOS/general-bus latch history remain incomplete.
The next timing work is Game Pak prefetch, with explicit startup and invalidation rules and independent tests.
The later [prefetch prerequisite](gamepak-prefetch.md) records source, data, internal, and refill costs in order without changing totals.
The next timing work remains an active Game Pak queue, with verified startup and invalidation rules and independent tests.