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refactor(cpu): account for timing in bus-access order

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0xrsydn 2026-10-06 17:16:08 +07:00
commit 7f3ebd3a5d
14 changed files with 626 additions and 65 deletions
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6
crates/gba-core/src/cpu/pipeline.rs
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@ -83,6 +83,12 @@ impl Cpu {
memory.fetch_instruction(pc, instruction_set),
memory.fetch_instruction(pc.wrapping_add(instruction_set.width()), instruction_set),
];
for (sample, kind) in fetches
.iter()
.zip([AccessKind::NonSequential, AccessKind::Sequential])
{
memory.record_code_access(sample.address(), instruction_set.access_width(), kind);
}
memory.refill_cpu_bus_history(&fetches);
self.pipeline = Some(Pipeline {
pc,