feat(serial): support disconnected Joybus configuration and local registers
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0xrsydn
parent
8b3b7ae62d
commit
7546d17630
15 changed files with 462 additions and 62 deletions
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@ -8,8 +8,8 @@ use crate::audio::Audio;
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pub use crate::audio::{FIFO_A, FIFO_B, SOUNDBIAS, SOUNDCNT_H, SOUNDCNT_X, SOUND_START, WAVE_RAM};
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pub(crate) use serial::Serial;
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pub use serial::{
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JOYCNT, JOY_RECV, JOY_TRANS, RCNT, SIOCNT, SIODATA32, SIODATA8, SIOMLT_SEND, SIOMULTI0,
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SIOMULTI1, SIOMULTI2, SIOMULTI3,
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JOYCNT, JOYSTAT, JOY_RECV, JOY_TRANS, RCNT, SIOCNT, SIODATA32, SIODATA8, SIOMLT_SEND,
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SIOMULTI0, SIOMULTI1, SIOMULTI2, SIOMULTI3,
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};
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mod timer_step;
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pub(crate) use timer_step::TimerStep;
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@ -1,4 +1,4 @@
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//! Disconnected serial: normal shifting and idle multiplayer child configuration.
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//! Disconnected serial: normal shifting, idle multiplayer, and local Joybus registers.
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use super::replace_byte;
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pub const SIODATA32: u32 = 0x0400_0120;
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@ -13,6 +13,7 @@ pub const RCNT: u32 = 0x0400_0134;
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pub const JOYCNT: u32 = 0x0400_0140;
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pub const JOY_RECV: u32 = 0x0400_0150;
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pub const JOY_TRANS: u32 = 0x0400_0154;
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pub const JOYSTAT: u32 = 0x0400_0158;
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#[derive(Debug, Default, Clone, Copy, PartialEq, Eq)]
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pub(crate) struct Serial {
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@ -21,6 +22,10 @@ pub(crate) struct Serial {
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send: u16, // Shared low byte; high byte is accessible only in multiplayer format.
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control: u16,
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rcnt: u16,
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joy_control: u8, // IRQ enable only; no external master can set event flags.
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joy_receive: u32,
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joy_transmit: u32,
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joy_status: u8, // Software flags and transmit pending; no remote reception.
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bits_left: u8,
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until_bit: u32,
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}
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@ -30,28 +35,28 @@ impl Serial {
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matches!(address,
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SIODATA32..=0x0400_012b |
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RCNT..=0x0400_0135 | JOYCNT..=0x0400_0141 |
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JOY_RECV..=0x0400_0157)
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JOY_RECV..=0x0400_0159)
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}
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pub(crate) fn unsupported(address: u32, value: u8) -> Option<&'static str> {
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match address {
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0x0400_0129 if value & 0x30 == 0x30 => Some("UART serial mode"),
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0x0400_0135 if value & 0xc0 == 0xc0 => Some("Joybus serial mode"),
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0x0400_0135 if value & 0x81 == 0x81 => Some("GPIO serial interrupt enable"),
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JOYCNT if value & 0x40 != 0 => Some("Joybus interrupt enable"),
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JOY_RECV..=0x0400_0157 if value != 0 => Some("Joybus data access beyond reset"),
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0x0400_0135 if value & 0xc1 == 0x81 => Some("GPIO serial interrupt enable"),
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_ => None,
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}
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}
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fn gpio(&self) -> bool {
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self.rcnt & 0x8000 != 0
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self.rcnt & 0xc000 == 0x8000
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}
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fn joybus(&self) -> bool {
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self.rcnt & 0xc000 == 0xc000
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}
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fn multiplayer_format(&self) -> bool {
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self.control & 0x3000 == 0x2000
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}
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fn normal(&self) -> bool {
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!self.gpio() && !self.multiplayer_format()
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self.rcnt & 0x8000 == 0 && !self.multiplayer_format()
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}
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fn busy(&self) -> bool {
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self.control & 0x80 != 0
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@ -137,7 +142,14 @@ impl Serial {
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.multiplayer_format()
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.then(|| self.multi_extra.to_le_bytes()[(address - SIOMULTI2) as usize]);
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}
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for (base, data) in [(JOY_RECV, self.joy_receive), (JOY_TRANS, self.joy_transmit)] {
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if (base..base + 4).contains(&address) {
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// No master can set receive status, so its read-clear bit is already zero.
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return Some(data.to_le_bytes()[(address - base) as usize]);
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}
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}
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let value = match address & !1 {
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SIOCNT if self.joybus() => self.control, // Unused; do not invent pin samples.
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SIOCNT => {
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let pins = if self.gpio() { self.gpio_pins() } else { 15 };
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// SI is pulled high without a cable. Multiplayer drives SD high while idle.
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@ -163,7 +175,8 @@ impl Serial {
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}
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(self.rcnt & !15) | self.gpio_pins()
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}
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JOYCNT | JOY_RECV..=0x0400_0156 => 0,
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JOYCNT => u16::from(self.joy_control),
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JOYSTAT => u16::from(self.joy_status),
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_ => return None,
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};
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Some(value.to_le_bytes()[(address & 1) as usize])
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@ -198,8 +211,22 @@ impl Serial {
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let shift = (at - SIOMULTI2) * 8;
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self.multi_extra =
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(self.multi_extra & !(255 << shift)) | (u32::from(value) << shift);
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} else if (JOY_RECV..JOY_TRANS).contains(&at) {
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// GBATEK describes R/W data latches. CPU writes are not remote events.
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let shift = (at - JOY_RECV) * 8;
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self.joy_receive =
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(self.joy_receive & !(255 << shift)) | (u32::from(value) << shift);
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} else if (JOY_TRANS..JOYSTAT).contains(&at) {
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let shift = (at - JOY_TRANS) * 8;
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self.joy_transmit =
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(self.joy_transmit & !(255 << shift)) | (u32::from(value) << shift);
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self.joy_status |= 2; // Data available, not transmission complete.
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} else {
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match at & !1 {
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JOYCNT if at & 1 == 0 => self.joy_control = value & 0x40,
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JOYSTAT if at & 1 == 0 => {
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self.joy_status = (self.joy_status & 2) | (value & 0x30);
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}
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SIODATA8 if self.multiplayer_format() || at & 1 == 0 => {
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self.send = replace_byte(self.send, at, value);
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}
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@ -15,6 +15,8 @@ mod iwram_bus;
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#[cfg(test)]
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mod iwram_history_tests;
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#[cfg(test)]
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mod joybus_step_tests;
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#[cfg(test)]
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mod multiplayer_step_tests;
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#[cfg(test)]
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mod prefetch_tests;
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91
crates/gba-core/src/memory/joybus_step_tests.rs
Normal file
91
crates/gba-core/src/memory/joybus_step_tests.rs
Normal file
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@ -0,0 +1,91 @@
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//! Original Joybus transaction, CPU access, and preflight regressions.
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use super::{timing_event_tests::prepared, *};
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use crate::{
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io::{IF, JOYCNT, JOYSTAT, JOY_RECV, JOY_TRANS, RCNT, SIOCNT},
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machine::Machine,
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};
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#[test]
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fn arm_and_thumb_transmit_stores_commit_pending_status_once() {
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for thumb in [false, true] {
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let (cpu, mut memory) = prepared(
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thumb,
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&[if thumb { 0x6008 } else { 0xe5810000 }], // STR r0,[r1]
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&[(0, 0x12345678), (1, JOY_TRANS)],
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);
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memory.write16(RCNT, 0xc000).unwrap();
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memory.write16(JOYCNT, 0x40).unwrap();
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let mut machine = Machine::new(cpu, memory);
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machine.step().unwrap();
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assert_eq!(machine.memory().read32(JOY_TRANS).unwrap(), 0x12345678);
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assert_eq!(machine.memory().read16(JOYSTAT).unwrap(), 2);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0);
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assert_eq!(machine.memory().io.serial.next_event_cycles(), None);
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}
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}
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#[test]
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fn joybus_mode_selection_observes_the_normal_completion_bus_phase() {
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for elapsed in [56, 57] {
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let (cpu, mut memory) = prepared(false, &[0xe5c10000], &[(0, 0xc1), (1, RCNT + 1)]);
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memory.write16(SIOCNT, 0x4083).unwrap();
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memory.advance_cycles(elapsed);
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let serial = memory.io.serial;
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let mut machine = Machine::new(cpu, memory);
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let cpu = machine.cpu().clone();
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if elapsed == 57 {
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machine.step().unwrap();
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assert_eq!(machine.cycles(), 64);
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assert_eq!(machine.memory().read8(RCNT + 1).unwrap(), 0xc1);
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assert_eq!(machine.memory().read16(IF).unwrap(), 0x80);
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assert_eq!(machine.memory().io.serial.next_event_cycles(), None);
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} else {
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let error = machine.step().unwrap_err();
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assert!(error.to_string().contains("serial reconfiguration"));
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assert_eq!(machine.step(), Err(error));
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assert_eq!(machine.cpu(), &cpu);
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assert_eq!(machine.cycles(), 56);
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assert_eq!(machine.memory().io.serial, serial);
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}
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}
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}
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#[test]
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fn later_block_padding_failure_discards_data_pending_status_and_writeback() {
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let (cpu, mut memory) = prepared(
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false,
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&[0xe8a0000e], // STMIA r0!,{r1-r3}; final word hits JOYSTAT padding.
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&[(0, JOY_RECV), (1, 0x12345678), (2, 0xabcdef90), (3, 0x30)],
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);
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memory.write16(RCNT, 0xc000).unwrap();
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let serial = memory.io.serial;
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let mut machine = Machine::new(cpu, memory);
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let cpu = machine.cpu().clone();
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let error = machine.step().unwrap_err();
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assert!(error.to_string().contains("0x0400015a"));
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assert_eq!(machine.step(), Err(error));
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assert_eq!(machine.cpu(), &cpu);
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assert_eq!(machine.cycles(), 0);
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assert_eq!(machine.memory().io.serial, serial);
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}
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#[test]
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fn staged_reads_see_transmit_pending_before_commit_and_discard_restores_every_lane() {
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let (_, mut memory) = prepared(false, &[0xe1a00000], &[]);
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let serial = memory.io.serial;
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memory.begin_timer_step();
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memory.write16(RCNT, 0xc100).unwrap();
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memory.write16(JOYCNT, 0x40).unwrap();
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memory.write32(JOY_TRANS, 0x12345678).unwrap();
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memory.write32(JOY_RECV, 0xabcdef90).unwrap();
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memory.write16(JOYSTAT, 0x30).unwrap();
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assert_eq!(memory.read32(JOY_TRANS).unwrap(), 0x12345678);
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assert_eq!(memory.read32(JOY_RECV).unwrap(), 0xabcdef90);
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assert_eq!(memory.read16(JOYSTAT).unwrap(), 0x32);
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assert_eq!(memory.read16(JOYCNT).unwrap(), 0x40);
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assert_eq!(memory.read8(RCNT), Err(MemoryError::Unmapped(RCNT)));
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assert_eq!(memory.io.serial, serial);
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memory.discard_timer_step();
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assert_eq!(memory.io.serial, serial);
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assert_eq!(memory.read16(JOYSTAT).unwrap(), 0);
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}
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