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feat(memory): retain IWRAM lane effects across DMA

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Update existing Thumb IWRAM continuation lanes from successful DMA reads and writes before the resumed PC+4 snapshot. Keep channel halfword duplication separate from actual lane accesses. Preserve atomic errors, cold-entry diagnostics, IRQ invalidation, and nominal timing.

Add original DMA matrices and resume regressions; update prior invalidation expectations. Record pinned ares and jgenesis evidence and explicit limits for cross-state history, general open bus, and sub-instruction arbitration.

Validated on Darwin arm64: 939 workspace and 870 core/demo tests per debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports remain identical to the previous results.
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0xrsydn 2026-10-06 02:34:58 +07:00
commit 663b25e5d1
15 changed files with 449 additions and 45 deletions
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docs/hardware/dma.md
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@ -55,8 +55,10 @@ DMA writes to DMA registers return `DmaError::RegisterDestination`; self-modifyi
Other accesses use the existing memory map, alignment checks, mirrors, and I/O write rules.
Other unmapped reads and cartridge writes remain diagnostics, not general DMA open-bus behavior.
A failed unit changes no memory, device state, or clock. Earlier units remain committed; the failed unit remains pending.
Successful units invalidate bounded sequential Thumb IWRAM history because DMA-to-CPU latch ordering is not modeled.
Failed units preserve that history. No DMA value is substituted for a CPU open-bus read.
Successful units update existing Thumb IWRAM continuation lanes for their actual IWRAM reads and writes, in that order.
Accesses elsewhere leave those local lanes unchanged. Failed units preserve history.
The resumed CPU's PC+4 fetch then updates its addressed halfword. No universal DMA-value override is used.
See [bounded IWRAM DMA history](cpu.md#dma-effects-on-thumb-iwram-continuations) for the scope.
## Retained channel data
@ -83,5 +85,5 @@ Earlier successful units remain committed. Normal destination validation, nomina
This error policy is not a model of hardware data aborts.
See [the latch evidence and scope](../research/dma-data-latches.md).
General DMA open-bus reads, IWRAM lane effects, and CPU bus ownership on resume remain unimplemented.
General DMA open-bus reads, cross-state IWRAM history, and sub-instruction bus ownership remain unimplemented.
In particular, the known channel value does not supply unused/write-only I/O reads or CPU open-bus snapshots.