feat(memory): retain IWRAM lane effects across DMA
Update existing Thumb IWRAM continuation lanes from successful DMA reads and writes before the resumed PC+4 snapshot. Keep channel halfword duplication separate from actual lane accesses. Preserve atomic errors, cold-entry diagnostics, IRQ invalidation, and nominal timing. Add original DMA matrices and resume regressions; update prior invalidation expectations. Record pinned ares and jgenesis evidence and explicit limits for cross-state history, general open bus, and sub-instruction arbitration. Validated on Darwin arm64: 939 workspace and 870 core/demo tests per debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports remain identical to the previous results.
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@ -128,7 +128,8 @@ See the [root-cause research](../research/bios-readback.md) for evidence and the
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Host/debug reads and ROM-suite memory assertions still inspect raw mapped bytes and do not initialize or change the history.
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Instruction fetches remain strict mapped reads outside the CPU data-access context.
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BIOS writes remain read-only diagnostics. DMA BIOS sources retain their existing unsupported-source diagnostic.
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BIOS writes remain read-only diagnostics. DMA BIOS sources never read image bytes.
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They reuse known [channel data](dma.md#retained-channel-data), or report an unsupported-source diagnostic when channel data is unknown.
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Missing BIOS images remain unmapped. The unused-memory ARM open-bus snapshot is separate from this retained BIOS value.
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The Thumb rule follows documented BIOS bus lanes and a source comparison with NanoBoyAdvance.
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