feat(memory): retain IWRAM lane effects across DMA
Update existing Thumb IWRAM continuation lanes from successful DMA reads and writes before the resumed PC+4 snapshot. Keep channel halfword duplication separate from actual lane accesses. Preserve atomic errors, cold-entry diagnostics, IRQ invalidation, and nominal timing. Add original DMA matrices and resume regressions; update prior invalidation expectations. Record pinned ares and jgenesis evidence and explicit limits for cross-state history, general open bus, and sub-instruction arbitration. Validated on Darwin arm64: 939 workspace and 870 core/demo tests per debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports remain identical to the previous results.
This commit is contained in:
0xrsydn
parent
e72c643640
commit
663b25e5d1
15 changed files with 449 additions and 45 deletions
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@ -22,6 +22,8 @@ mod exception_tests;
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#[cfg(test)]
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mod instruction_tests;
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#[cfg(test)]
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mod iwram_dma_tests;
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#[cfg(test)]
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mod iwram_open_bus_tests;
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#[cfg(test)]
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mod iwram_refill_tests;
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314
crates/gba-core/src/cpu/iwram_dma_tests.rs
Normal file
314
crates/gba-core/src/cpu/iwram_dma_tests.rs
Normal file
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@ -0,0 +1,314 @@
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//! Original instruction-boundary DMA/IWRAM history tests, not sub-instruction arbitration.
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use super::*;
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use crate::{
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dma::{DMA_BASE, DMA_STRIDE},
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io::{IE, IME, TIMER_BASE},
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machine::{Machine, StepKind},
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};
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const CODE: u32 = 0x0300_0100;
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const IWRAM: u32 = 0x0300_1000;
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const EWRAM: u32 = 0x0200_1000;
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const SEED: u32 = 0x1234_abcd;
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const DATA: u32 = 0x97e6_b580;
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const NEXT: u16 = 0xd238;
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const PROBE: u16 = 0x6806; // LDR r6,[r0]
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const UNUSED: u32 = 0x8000_0000;
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fn program(pc: u32, first: u16) -> (Cpu, Memory) {
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let mut bus = Memory::new(vec![]).unwrap();
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for (i, half) in [first, PROBE, 0x4321, NEXT].into_iter().enumerate() {
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bus.write16(pc + i as u32 * 2, half).unwrap();
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}
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bus.write32(IWRAM, SEED).unwrap();
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let mut cpu = Cpu::new(pc);
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cpu.instruction_set = InstructionSet::Thumb;
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cpu.registers[0] = UNUSED;
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cpu.registers[1] = IWRAM;
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(cpu, bus)
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}
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fn ready(pc: u32) -> Machine {
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let (cpu, bus) = program(pc, 0x680a); // LDR r2,[r1] establishes both lanes.
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let mut machine = Machine::new(cpu, bus);
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machine.step().unwrap();
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machine
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}
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fn configure(
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bus: &mut Memory,
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channel: usize,
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source: u32,
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destination: u32,
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count: u16,
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word: bool,
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) {
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let base = DMA_BASE + channel as u32 * DMA_STRIDE;
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bus.write16(base + 10, 0).unwrap(); // Disable before rearming.
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bus.write32(base, source).unwrap();
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bus.write32(base + 4, destination).unwrap();
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bus.write32(
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base + 8,
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(if word { 0x8400_0000 } else { 0x8000_0000 }) | u32::from(count),
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)
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.unwrap();
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}
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fn transfer(machine: &mut Machine, source: u32, destination: u32, word: bool) {
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configure(machine.memory_mut(), 3, source, destination, 1, word);
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let cpu = machine.cpu().clone();
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 3 });
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assert_eq!(machine.cpu(), &cpu);
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}
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// Independent byte-array reference. Only page 3 drives the local IWRAM lanes.
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fn drive(lanes: &mut [u8; 4], address: u32, bytes: &[u8]) {
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if address >> 24 == 3 {
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let start = (address & 3) as usize;
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lanes[start..start + bytes.len()].copy_from_slice(bytes);
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}
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}
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fn resumed(lanes: [u8; 4], pc: u32) -> u32 {
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let mut lanes = lanes;
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drive(&mut lanes, pc + 6, &NEXT.to_le_bytes());
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u32::from_le_bytes(lanes)
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}
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#[test]
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fn dma_source_and_destination_drive_only_addressed_iwram_lanes_before_resume_fetch() {
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for pc in [CODE, CODE + 2, CODE + 0x8000, 0x0300_7ffc, 0x0300_7ffe] {
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for word in [false, true] {
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for source in [IWRAM + 0x8000, IWRAM + 0x8002, EWRAM, EWRAM + 2] {
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for destination in [IWRAM + 0x100, IWRAM + 0x102, EWRAM + 0x100, EWRAM + 0x102] {
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let width = if word { 4 } else { 2 };
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let source = source & !(width - 1);
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let destination = destination & !(width - 1);
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let mut machine = ready(pc);
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machine.memory_mut().write32(source & !3, DATA).unwrap();
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let bytes = DATA.to_le_bytes();
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let lane = (source & 3) as usize;
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let bytes = &bytes[lane..lane + width as usize];
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let mut expected = SEED.to_le_bytes();
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drive(&mut expected, source, bytes);
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drive(&mut expected, destination, bytes);
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transfer(&mut machine, source, destination, word);
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// Host reads/writes after DMA cannot replace retained lanes.
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machine.memory_mut().write32(source & !3, 0).unwrap();
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machine.memory().read32(destination & !3).unwrap();
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[6], resumed(expected, pc));
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}
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}
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}
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}
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}
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#[test]
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fn halfword_channel_duplication_is_not_a_full_iwram_bus_write() {
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let mut machine = ready(CODE);
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machine.memory_mut().write32(IWRAM, DATA).unwrap();
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// High source lane only: low IWRAM bus lane must retain SEED's low half.
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transfer(&mut machine, IWRAM + 2, EWRAM, false);
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machine.step().unwrap();
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assert_eq!(
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machine.cpu().registers()[6],
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(u32::from(NEXT) << 16) | (SEED & 0xffff)
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);
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}
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#[test]
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fn blocked_source_updates_only_the_destination_lane_using_its_selected_channel_half() {
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for pc in [CODE, CODE + 2] {
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for destination in [IWRAM + 0x100, IWRAM + 0x102, EWRAM + 0x100] {
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let mut machine = ready(pc);
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machine.memory_mut().write32(EWRAM, DATA).unwrap();
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transfer(&mut machine, EWRAM, EWRAM + 8, true); // Seed channel without touching IWRAM.
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transfer(&mut machine, 2, destination, false);
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let half = (DATA >> ((destination & 2) * 8)) as u16;
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let mut expected = SEED.to_le_bytes();
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drive(&mut expected, destination, &half.to_le_bytes());
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[6], resumed(expected, pc));
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assert_eq!(machine.memory().read16(destination).unwrap(), half);
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}
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}
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}
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#[test]
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fn completed_units_and_priority_changes_use_access_order_not_channel_number() {
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let mut machine = ready(CODE);
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machine.memory_mut().write32(EWRAM, DATA).unwrap();
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machine
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.memory_mut()
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.write32(EWRAM + 4, 0x7612_8abc)
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.unwrap();
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machine
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.memory_mut()
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.write32(EWRAM + 8, 0xaabb_eeff)
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.unwrap();
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configure(machine.memory_mut(), 3, EWRAM, IWRAM, 2, true);
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 3 });
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configure(machine.memory_mut(), 0, EWRAM + 8, IWRAM + 8, 1, true);
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for channel in [0, 3] {
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel });
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}
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machine.step().unwrap();
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assert_eq!(
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machine.cpu().registers()[6],
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resumed(0x7612_8abc_u32.to_le_bytes(), CODE)
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);
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}
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#[test]
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fn failed_dma_and_failed_resumed_instruction_preserve_last_completed_dma_history() {
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for fail_destination in [false, true] {
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let mut machine = ready(CODE);
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machine.memory_mut().write32(EWRAM, DATA).unwrap();
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transfer(&mut machine, EWRAM, IWRAM, true);
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// A valid IWRAM source must not drive history if its destination is invalid.
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machine.memory_mut().write32(IWRAM, 0x1122_3344).unwrap();
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configure(
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machine.memory_mut(),
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3,
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if fail_destination { IWRAM } else { 0x0e00_0000 },
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if fail_destination { 0x0800_0000 } else { IWRAM },
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1,
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true,
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);
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let before = machine.cpu().clone();
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let cycles = machine.cycles();
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let timing = machine.last_timing();
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for _ in 0..2 {
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assert!(machine.step().is_err());
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.last_timing(), timing);
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}
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machine
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.memory_mut()
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.write16(DMA_BASE + 3 * DMA_STRIDE + 10, 0)
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.unwrap();
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machine.memory_mut().write16(CODE + 2, 0xde00).unwrap(); // Unsupported instruction.
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assert!(machine.step().is_err());
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.cycles(), cycles);
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machine.memory_mut().write16(CODE + 2, PROBE).unwrap();
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machine.step().unwrap();
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assert_eq!(
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machine.cpu().registers()[6],
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resumed(DATA.to_le_bytes(), CODE)
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);
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}
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}
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#[test]
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fn partial_continuation_can_gain_known_lanes_but_cold_direct_entry_stays_unknown() {
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let (mut cpu, mut bus) = program(CODE, 0x46c0); // NOP fills only the low lane.
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cpu.step(&mut bus).unwrap();
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bus.write32(EWRAM, DATA).unwrap();
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configure(&mut bus, 3, EWRAM, IWRAM, 1, true);
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bus.step_dma().unwrap().unwrap();
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cpu.step(&mut bus).unwrap();
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assert_eq!(cpu.registers[6], resumed(DATA.to_le_bytes(), CODE));
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// No executed instruction or refill established an expected continuation PC.
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let (mut cpu, mut bus) = program(CODE, PROBE);
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bus.write32(EWRAM, DATA).unwrap();
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configure(&mut bus, 3, EWRAM, IWRAM, 1, true);
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bus.step_dma().unwrap().unwrap();
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assert_eq!(
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cpu.step(&mut bus),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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}
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#[test]
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fn irq_and_pc_discontinuity_do_not_reuse_dma_updated_continuations() {
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for irq in [false, true] {
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let mut machine = ready(CODE);
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machine.memory_mut().write32(EWRAM, DATA).unwrap();
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transfer(&mut machine, EWRAM, IWRAM, true);
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let mut cpu = machine.cpu().clone();
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if irq {
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machine.memory_mut().write16(IE, 8).unwrap();
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machine.memory_mut().write16(IME, 1).unwrap();
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machine
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.memory_mut()
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.write32(TIMER_BASE, 0x00c0_ffff)
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.unwrap();
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machine.memory_mut().advance_cycles(1);
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assert_eq!(machine.step().unwrap(), StepKind::IrqEntry);
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} else {
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cpu.registers[15] = CODE + 0x100;
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machine.memory_mut().write16(cpu.pc(), PROBE).unwrap();
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}
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assert_eq!(
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cpu.step(machine.memory_mut()),
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Err(CpuError::Memory(MemoryError::Unmapped(UNUSED)))
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);
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}
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}
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#[test]
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fn arm_and_other_thumb_regions_keep_their_fetch_snapshot_not_dma_data() {
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for thumb in [false, true] {
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for pc in [0x0200_0100, 0x0300_0100, 0x0700_0100] {
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if thumb && pc >> 24 == 3 {
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continue; // The bounded IWRAM continuation is tested separately.
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}
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let mut bus = Memory::new(vec![]).unwrap();
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let mut cpu = Cpu::new(pc);
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cpu.registers[0] = UNUSED;
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let expected = if thumb {
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cpu.instruction_set = InstructionSet::Thumb;
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bus.write16(pc, PROBE).unwrap();
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bus.write32(pc + 4, 0x83e6_92ab).unwrap();
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if pc >> 24 == 7 {
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0x83e6_92ab
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} else {
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0x92ab_92ab
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}
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} else {
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bus.write32(pc, 0xe590_6000).unwrap(); // LDR r6,[r0].
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bus.write32(pc + 8, 0x83e6_92ab).unwrap();
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0x83e6_92ab
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};
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bus.write32(EWRAM, DATA).unwrap();
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let mut machine = Machine::new(cpu, bus);
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transfer(&mut machine, EWRAM, IWRAM, true);
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machine.step().unwrap();
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assert_eq!(machine.cpu().registers()[6], expected);
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}
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}
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}
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#[test]
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fn history_changes_add_no_timing_and_match_timed_and_untimed_cpu_results() {
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let mut machine = ready(CODE);
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machine
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.memory_mut()
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.write32(TIMER_BASE, 0x0080_0000)
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.unwrap();
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let start = machine.cycles();
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machine.memory_mut().write32(EWRAM, DATA).unwrap();
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transfer(&mut machine, EWRAM, IWRAM, true);
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assert_eq!(machine.last_timing().code_cycles, 0);
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assert_eq!(machine.last_timing().data_cycles, 7);
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assert_eq!(machine.last_timing().internal_cycles, 2);
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machine.step().unwrap();
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assert_eq!(machine.last_timing().code_cycles, 1);
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assert_eq!(machine.last_timing().data_cycles, 1);
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assert_eq!(machine.last_timing().internal_cycles, 1);
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assert_eq!(machine.cycles() - start, 12);
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assert_eq!(machine.memory().read16(TIMER_BASE).unwrap(), 12);
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let (mut cpu, mut bus) = program(CODE, 0x680a);
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cpu.step(&mut bus).unwrap();
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bus.write32(EWRAM, DATA).unwrap();
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configure(&mut bus, 3, EWRAM, IWRAM, 1, true);
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bus.step_dma().unwrap().unwrap();
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cpu.step(&mut bus).unwrap();
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assert_eq!(&cpu, machine.cpu());
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assert_eq!(bus.cycles(), 9); // Only explicit DMA stepping advances clocks here.
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}
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@ -338,7 +338,7 @@ fn pc_discontinuities_and_non_iwram_execution_do_not_reuse_old_history() {
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}
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#[test]
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fn successful_dma_invalidates_history_but_failed_dma_preserves_it() {
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fn successful_dma_updates_history_and_failed_dma_preserves_it() {
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for fail in [false, true] {
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let (cpu, mut bus) = program(CODE, &[SEED, PROBE, 0x1111, 0x9bcd]);
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bus.write32(TIMER_BASE, 0x0080_0000).unwrap();
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@ -364,8 +364,9 @@ fn successful_dma_invalidates_history_but_failed_dma_preserves_it() {
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.memory().read32(0x0200_0000).unwrap(), DATA);
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let cycles = machine.cycles();
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assert!(machine.step().is_err());
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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assert_eq!(machine.cpu().registers()[6], 0x9bcd_80a5);
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assert_eq!(machine.cycles(), cycles + 3);
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}
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assert_eq!(
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u64::from(machine.memory().read16(TIMER_BASE).unwrap()),
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@ -3,7 +3,7 @@ use super::*;
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use crate::{
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dma::{DMA_BASE, DMA_STRIDE},
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io::{IE, IME, TIMER_BASE},
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machine::{Machine, MachineError, StepKind},
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machine::{Machine, StepKind},
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memory::{BIOS_SIZE, ROM_START},
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};
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@ -373,7 +373,7 @@ fn target_pair_refill_does_not_replace_the_separate_bios_retained_word() {
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}
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#[test]
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fn successful_dma_between_refill_and_target_execution_invalidates_refill_history() {
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fn successful_dma_between_refill_and_target_execution_updates_refill_history() {
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let (cpu, mut bus) = branch(ROM_START, false, TARGET);
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bus.write32(STACK, 0x1234_abcd).unwrap();
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let mut machine = Machine::new(cpu, bus);
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@ -383,19 +383,12 @@ fn successful_dma_between_refill_and_target_execution_invalidates_refill_history
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machine.memory_mut().write32(dma + 4, 0x0200_0000).unwrap();
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machine.memory_mut().write32(dma + 8, 0x8400_0001).unwrap();
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assert_eq!(machine.step().unwrap(), StepKind::Dma { channel: 3 });
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let before = machine.cpu().clone();
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let timing = machine.last_timing();
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let cycles = machine.cycles();
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assert_eq!(
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machine.step(),
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Err(MachineError::Cpu(CpuError::Memory(MemoryError::Unmapped(
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UNUSED
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))))
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);
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assert_eq!(machine.cpu(), &before);
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assert_eq!(machine.last_timing(), timing);
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assert_eq!(machine.cycles(), cycles);
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assert_eq!(machine.cpu().pc(), TARGET);
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assert_eq!(machine.step().unwrap(), StepKind::Instruction);
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// DMA reads the whole IWRAM word, then the target+4 fetch replaces its low half.
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assert_eq!(machine.cpu().registers()[6], 0x1234_d234);
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assert_eq!(machine.cycles(), cycles + 3);
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assert_eq!(machine.cpu().pc(), TARGET + 2);
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}
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#[test]
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|
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@ -67,7 +67,8 @@ struct CpuAccess {
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/// Protected BIOS reads separately retain the snapshot from BIOS execution.
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/// Sequential Thumb IWRAM accesses retain addressed bus lanes transactionally.
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/// Successful refills into Thumb IWRAM sample the target pair to establish history.
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/// DMA channels retain transfer data separately; CPU bus handoff remains unmodeled.
|
||||
/// DMA accesses drive existing Thumb IWRAM continuation lanes before the next fetch.
|
||||
/// Channel data remains separate; general and sub-instruction CPU bus handoff is unmodeled.
|
||||
/// A full fetch pipeline and ARM-target refill history are not modeled.
|
||||
pub struct Memory {
|
||||
external_ram: Vec<u8>,
|
||||
|
|
@ -329,8 +330,13 @@ impl Memory {
|
|||
AccessWidth::Byte => unreachable!("DMA is never byte-wide"),
|
||||
}
|
||||
.map_err(map_error)?;
|
||||
// DMA-to-CPU bus ordering is not modeled. Never reuse pre-DMA IWRAM history.
|
||||
self.invalidate_cpu_bus_history();
|
||||
// DMA runs before the resumed CPU fetch. Only actual IWRAM accesses drive
|
||||
// its local lanes, in read/write order. Channel halfword duplication is not
|
||||
// a full IWRAM bus write. Failed units never reach these history commits.
|
||||
self.iwram_bus
|
||||
.dma_access(transfer.source, transfer.width, data_latch);
|
||||
self.iwram_bus
|
||||
.dma_access(transfer.destination, transfer.width, value);
|
||||
// Keep this channel active during its cycles: another edge must not
|
||||
// queue a second block while the current block is still transferring.
|
||||
self.advance_cycles(timing.total());
|
||||
|
|
|
|||
|
|
@ -1,5 +1,6 @@
|
|||
//! Transactional lane history for Thumb IWRAM execution and target-pair refills.
|
||||
//! Unknown startup/DMA history is not replaced with guessed memory bytes.
|
||||
//! Completed DMA accesses update existing continuation lanes before the next fetch.
|
||||
//! Unknown startup history is not replaced with guessed memory bytes.
|
||||
use std::cell::Cell;
|
||||
|
||||
use crate::timing::AccessWidth;
|
||||
|
|
@ -76,6 +77,17 @@ impl IwramBus {
|
|||
}
|
||||
}
|
||||
|
||||
/// DMA runs between instructions. Commit only after the entire unit succeeds.
|
||||
/// Keep the expected CPU continuation PC; do not invent one at cold startup.
|
||||
pub(super) fn dma_access(&mut self, address: u32, width: AccessWidth, value: u32) {
|
||||
debug_assert!(self.pending.get().is_none());
|
||||
if address >> 24 == 3 {
|
||||
if let Some(history) = &mut self.committed {
|
||||
history.lanes.drive(address, width, value);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(super) fn finish(&mut self, succeeded: bool, sequential: bool) {
|
||||
let pending = self.pending.take();
|
||||
if succeeded {
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue