test(memory): integrate pinned public memory compatibility suite
Add --suite memory with verified source hashes, ARM eval checkpoint 0x08000350, and the r12 result assertion. Keep default ARM and explicit Thumb preparation unchanged. Extend offline adapter and CLI tests; retain public binaries outside tracked files. The unmodified memory ROM passes in debug and release after 174 steps and 1478 nominal cycles, without changing core behavior. Document weak byte-write assertions and mode-selection caveats. Add original CPU-driven tests with exact sentinels, mode/mirror boundaries, byte lanes, forced blank, readback, and nominal device timing. Validated on Darwin arm64: 851 workspace tests in debug and release; 782 core/demo tests separately; 30 Python tests; all three pinned public suites in both profiles; native ROM windows; all ten demo smoke tests; fmt, clippy, rustdoc, and local documentation links.
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@ -51,6 +51,7 @@ Its tests verify manifest limits, whole-suite validation, exact step boundaries,
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Additional tests cover DMA/IRQ accounting, HALT/STOP, diagnostic state, case isolation, repeatable JSON output, and failure exit status.
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These original tests validate the runner. The [public ARM adapter](public-arm-tests.md) provides a separate passing checkpoint result for its pinned ROM.
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The [public Thumb adapter](public-thumb-tests.md) uses a separate lock and r7 assertion after its return to ARM state.
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The [public memory adapter](public-memory-tests.md) uses its own lock and an ARM-state r12 checkpoint.
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Preparation tests use only synthetic original bytes and no network:
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```sh
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@ -58,7 +59,7 @@ direnv exec . python3 -B -m unittest discover -s tools -p 'test_*.py' -v
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```
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They verify suite selection, pinned URLs, hashes, sizes, checkpoint validation, offline copies, destination safety, and non-overwriting output.
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Thumb cases also verify the return-to-ARM bridge. Command-line tests cover default ARM selection, explicit Thumb selection, and errors.
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Thumb cases also verify the return-to-ARM bridge. Command-line tests cover default ARM selection, explicit Thumb/memory selection, and errors.
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Compare/status CPU regressions verify saved flags/masks, bank switching, sequential PC/timing, User/System fallback, and atomic diagnostics.
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Load-alias regressions cover widths, signed/unaligned values, immediate/register offsets, pre/post-indexing, every non-PC register bank, and address wrapping.
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They verify loaded-value precedence, preserved flags, unchanged stores, nominal timing, I/O reads before device progress, deferred IRQ delivery, and atomic errors.
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@ -69,7 +70,12 @@ The pinned public Thumb ROM also reaches its ARM-state checkpoint with r7 = 0 in
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Empty-list Thumb regressions cover PC+6, all low bases and processor modes, banked stacks, both code alignments, and unaligned data.
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They check one-word writes, 64-byte writeback, ROM windows, the following PC operand, nominal timing, and atomic errors.
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Existing ARM empty-list and Thumb empty-load tests continue to pass. `PUSH {lr}` retains its normal link value.
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These results do not establish public timing, memory, graphics, BIOS, or commercial-game compatibility.
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The pinned public memory ROM also passes in both builds, but its video-byte assertions and mode selection have documented limits.
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Separate original CPU tests check exact video-byte results across supported modes, mirrored addresses, byte lanes, and boundaries.
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They require unchanged nonzero sentinels for ignored writes and unchanged adjacent halfwords for duplicated writes.
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They also check forced blank, full source-value preservation, CPU halfword readback, nominal data costs, and device progress.
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Halfword/word stores remain writable in object regions. No emulator behavior change was needed for these tests.
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These results do not establish public timing, graphics, BIOS, save, or commercial-game compatibility.
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ROM-runner tests use temporary files containing original instructions, without Nintendo assets or a desktop session.
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They check file-size boundaries, bounded reads, short reads, I/O errors, paths, symlinks, and read-only loading.
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