feat(input): implement KEYCNT keypad interrupt control
Add a dependency-free keypad state machine in gba-core, map KEYCNT, latch IF bit 12, and wake HALT through the existing interrupt gates. Sample complete CPU/DMA control writes once so transient byte values cannot create false requests. Document the mGBA-style polling policy and its unverified hardware retrigger limits. Cover every button-state/selection pair, register masks, repeated requests, byte/word writes, failed-store isolation, DMA priority, ARM/Thumb IRQ return, BIOS IntrWait, and retained BIOS reset state. Follow the restructured workspace and modular documentation. Validated on Darwin arm64: workspace and core/demo tests pass in debug and release, with Clippy, rustdoc, ten native window smoke tests, and terminal demos passing.
This commit is contained in:
parent
7d396fea35
commit
597b02881b
14 changed files with 710 additions and 21 deletions
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@ -4,7 +4,7 @@ use gba_core::{
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dma::{DmaError, DMA_BASE, DMA_STRIDE},
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input::Buttons,
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io::{
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BG0CNT, BG2PA, BG2PD, BG3PA, BG3PD, BLDALPHA, BLDCNT, DISPCNT, GREENSWAP, KEYINPUT,
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BG0CNT, BG2PA, BG2PD, BG3PA, BG3PD, BLDALPHA, BLDCNT, DISPCNT, GREENSWAP, KEYCNT, KEYINPUT,
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WAITCNT, WININ, WINOUT,
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},
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memory::{OAM_START, PALETTE_START},
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@ -236,6 +236,7 @@ fn io_reset_clears_readable_controls_but_keeps_input_postflg_and_green_swap() {
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let (mut m, pc) = prepare(flags, false, 0x9f);
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m.memory_mut().set_buttons(Buttons::from_bits(0x251));
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let keys = m.memory().read16(KEYINPUT).unwrap();
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m.memory_mut().write16(KEYCNT, 0x4001).unwrap();
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m.memory_mut().write16(GREENSWAP, 1).unwrap();
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for address in [
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BG0CNT,
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@ -277,6 +278,7 @@ fn io_reset_clears_readable_controls_but_keeps_input_postflg_and_green_swap() {
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}
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assert_eq!(m.memory().read16(DISPSTAT).unwrap() & 0xff38, 0);
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assert_eq!(m.memory().read16(KEYINPUT).unwrap(), keys);
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assert_eq!(m.memory().read16(KEYCNT).unwrap(), 0x4001); // Current reset subset preserves KEYCNT.
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assert_eq!(m.memory().read16(POSTFLG).unwrap(), 1);
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assert_eq!(m.memory().read16(GREENSWAP).unwrap(), 1);
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assert!(m.cycles() > cycles);
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@ -279,10 +279,7 @@ fn keyinput_exposes_all_ten_buttons_active_low_and_ignores_writes() {
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memory.set_buttons(Buttons::default());
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assert_eq!(memory.read16(KEYINPUT).unwrap(), 0x3ff);
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assert_eq!(memory.cycles(), 0);
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assert_eq!(
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memory.read16(KEYINPUT + 2),
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Err(MemoryError::Unmapped(KEYINPUT + 2))
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); // KEYCNT deferred.
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assert_eq!(memory.read16(KEYINPUT + 2).unwrap(), 0); // KEYCNT resets disabled.
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}
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#[test]
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498
crates/gba-core/tests/keypad.rs
Normal file
498
crates/gba-core/tests/keypad.rs
Normal file
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@ -0,0 +1,498 @@
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use gba_core::{
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bios,
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cpu::{Cpu, CpuError, InstructionSet, Mode},
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dma::DMA_BASE,
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input::Buttons,
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io::{HALTCNT, IE, IF, IME, KEYCNT, KEYINPUT, TIMER_BASE},
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machine::{Machine, MachineError, StepKind},
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memory::{Memory, MemoryError, BIOS_SIZE, ROM_START},
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};
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const IRQ: u16 = 1 << 12;
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fn words(code: &[u32]) -> Vec<u8> {
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code.iter().flat_map(|v| v.to_le_bytes()).collect()
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}
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fn bus() -> Memory {
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Memory::new(vec![]).unwrap()
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}
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fn press(m: &mut Memory, buttons: u16) {
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m.set_buttons(Buttons::from_bits(buttons));
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}
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fn pending(m: &Memory) -> bool {
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m.read16(IF).unwrap() & IRQ != 0
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}
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fn ack(m: &mut Memory) {
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m.write16(IF, IRQ).unwrap();
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assert!(!pending(m));
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}
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#[test]
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fn register_reset_masks_byte_merges_and_combined_word_access() {
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let mut m = bus();
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assert_eq!(m.read32(KEYINPUT).unwrap(), 0x03ff);
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for value in 0..=u16::MAX {
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m.write16(KEYCNT, value).unwrap();
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assert_eq!(m.read16(KEYCNT).unwrap(), value & 0xc3ff);
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}
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m.write16(KEYCNT, 0).unwrap();
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m.write8(KEYCNT + 1, 0xff).unwrap();
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assert_eq!(m.read16(KEYCNT).unwrap(), 0xc300);
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m.write8(KEYCNT, 0xa5).unwrap();
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assert_eq!(m.read16(KEYCNT).unwrap(), 0xc3a5);
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assert_eq!(m.read8(KEYCNT).unwrap(), 0xa5);
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assert_eq!(m.read8(KEYCNT + 1).unwrap(), 0xc3);
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press(&mut m, 0x201);
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m.write32(KEYINPUT, 0x0123_ffff).unwrap();
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assert_eq!(m.read32(KEYINPUT).unwrap(), 0x0123_01fe);
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m.write16(KEYINPUT, 0).unwrap();
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assert_eq!(m.read32(KEYINPUT).unwrap(), 0x0123_01fe);
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assert_eq!(m.cycles(), 0);
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assert_eq!(m.read32(KEYCNT), Err(MemoryError::Unaligned(KEYCNT)));
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for address in [KEYCNT + 2, KEYCNT + 0x400] {
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assert_eq!(m.read8(address), Err(MemoryError::Unmapped(address)));
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assert_eq!(m.write8(address, 0), Err(MemoryError::Unmapped(address)));
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}
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}
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#[test]
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fn every_button_can_request_irq_independently_of_ie_and_ime() {
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for bit in 0..10 {
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for mode in [0, 0x8000] {
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let mut m = bus();
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m.write16(KEYCNT, 0x4000 | mode | (1 << bit)).unwrap();
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for other in 0..10 {
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press(&mut m, if other == bit { 0 } else { 1 << other });
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assert!(!pending(&m));
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}
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press(&mut m, 1 << bit);
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assert!(pending(&m));
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assert!(!m.irq_pending());
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m.write16(IE, IRQ).unwrap();
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assert!(!m.irq_pending());
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m.write16(IME, 1).unwrap();
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assert!(m.irq_pending());
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}
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}
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}
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#[test]
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fn or_mode_requests_on_each_matching_input_sample_but_not_on_clock_updates() {
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let mut m = bus();
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m.write16(KEYCNT, 0x4003).unwrap();
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for buttons in [1, 1, 3, 2, 2] {
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press(&mut m, buttons);
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assert!(pending(&m));
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ack(&mut m);
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m.advance_cycles(12345);
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assert!(!pending(&m));
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assert_eq!(m.read16(KEYCNT).unwrap(), 0x4003);
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}
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press(&mut m, 4);
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assert!(!pending(&m));
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press(&mut m, 0);
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assert!(!pending(&m));
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}
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#[test]
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fn and_mode_requires_selected_keys_but_allows_extra_keys_and_suppresses_identical_samples() {
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let mut m = bus();
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m.write16(KEYCNT, 0xc003).unwrap();
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for buttons in [0, 1, 2, 4] {
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press(&mut m, buttons);
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assert!(!pending(&m));
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}
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for buttons in [3, 7, 3] {
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press(&mut m, buttons);
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assert!(pending(&m)); // Includes changes to unselected keys in the polling model.
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ack(&mut m);
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press(&mut m, buttons);
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assert!(!pending(&m));
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m.write16(KEYCNT, 0xc003).unwrap();
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assert!(!pending(&m));
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}
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press(&mut m, 1);
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assert!(!pending(&m));
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press(&mut m, 3);
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assert!(pending(&m));
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}
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#[test]
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fn empty_masks_follow_boolean_or_and_rules() {
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for buttons in [0, 1, 0x3ff] {
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let mut m = bus();
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press(&mut m, buttons);
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m.write16(KEYCNT, 0x4000).unwrap();
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assert!(!pending(&m));
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m.write16(KEYCNT, 0xc000).unwrap();
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assert!(pending(&m));
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ack(&mut m);
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press(&mut m, buttons);
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assert!(!pending(&m));
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}
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}
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#[test]
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fn held_keys_are_sampled_on_control_writes_and_new_selection_rearms_and() {
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let mut m = bus();
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press(&mut m, 3);
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m.write16(KEYCNT, 0x0001).unwrap();
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assert!(!pending(&m));
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m.write16(KEYCNT, 0xc001).unwrap();
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assert!(pending(&m));
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ack(&mut m);
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m.write16(KEYCNT, 0xc003).unwrap();
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assert!(pending(&m)); // B was newly selected while already held.
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ack(&mut m);
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m.write16(KEYCNT, 0xc003).unwrap();
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assert!(!pending(&m));
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m.write16(KEYCNT, 0xc007).unwrap();
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assert!(!pending(&m)); // Newly selected, but not all selected keys held.
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m.write16(KEYCNT, 0xc003).unwrap();
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assert!(pending(&m));
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}
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#[test]
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fn disabling_or_releasing_keys_does_not_acknowledge_if_and_disabled_sampling_keeps_history() {
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let mut m = bus();
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press(&mut m, 1);
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m.write16(KEYCNT, 0xc001).unwrap();
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assert!(pending(&m));
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m.write16(KEYCNT, 0x8001).unwrap();
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press(&mut m, 0);
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assert!(pending(&m));
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ack(&mut m);
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press(&mut m, 1);
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m.write16(KEYCNT, 0xc001).unwrap();
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assert!(!pending(&m)); // No matching-state history update while disabled.
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press(&mut m, 0);
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press(&mut m, 1);
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assert!(pending(&m));
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}
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#[test]
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fn halfword_and_word_control_writes_never_sample_intermediate_byte_values() {
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for word in [false, true] {
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for (old, new, buttons) in [(0x4002, 0x0001, 1), (0xc001, 0x4000, 0)] {
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let mut m = bus();
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press(&mut m, buttons);
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m.write16(KEYCNT, old).unwrap();
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assert!(!pending(&m));
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if word {
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m.write32(KEYINPUT, u32::from(new) << 16).unwrap();
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} else {
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m.write16(KEYCNT, new).unwrap();
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}
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assert!(!pending(&m));
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assert_eq!(m.read16(KEYCNT).unwrap(), new);
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}
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}
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// Separate byte stores really do expose the intermediate enabled mask.
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let mut m = bus();
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press(&mut m, 1);
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m.write16(KEYCNT, 0x4002).unwrap();
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m.write8(KEYCNT, 1).unwrap();
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assert!(pending(&m));
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m.write8(KEYCNT + 1, 0).unwrap();
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assert!(pending(&m));
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}
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#[test]
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fn keyinput_writes_and_reads_do_not_resample_an_acknowledged_request() {
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let mut m = bus();
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m.write16(KEYCNT, 0x4001).unwrap();
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press(&mut m, 1);
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ack(&mut m);
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m.write8(KEYINPUT, 0).unwrap();
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m.write8(KEYINPUT + 1, 0).unwrap();
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m.write16(KEYINPUT, 0).unwrap();
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assert_eq!(m.read16(KEYINPUT).unwrap(), 0x3fe);
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assert_eq!(m.read32(KEYINPUT).unwrap(), 0x4001_03fe);
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assert!(!pending(&m));
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// An actual KEYCNT write is a new sample, even if its value is unchanged.
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m.write16(KEYCNT, 0x4001).unwrap();
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assert!(pending(&m));
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}
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fn machine(masked: bool) -> Machine {
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let mut m = Machine::new(
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Cpu::new(ROM_START),
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Memory::new(words(&[
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if masked { 0xe321_f09f } else { 0xe321_f01f },
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0xe280_0001,
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0xeaff_fffe,
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]))
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.unwrap(),
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);
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m.step().unwrap();
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m
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}
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#[test]
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fn keypad_wakes_halt_only_through_ie_and_ignores_ime_and_cpu_masks_for_wake() {
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for masked in [false, true] {
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for ie in [0, IRQ] {
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for ime in [0, 1] {
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let mut m = machine(masked);
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m.memory_mut().write16(KEYCNT, 0x4001).unwrap();
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m.memory_mut().write16(IE, ie).unwrap();
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m.memory_mut().write16(IME, ime).unwrap();
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m.memory_mut().write8(HALTCNT, 0).unwrap();
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let before = m.cpu().clone();
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let cycles = m.cycles();
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let timing = m.last_timing();
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press(m.memory_mut(), 1);
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assert!(pending(m.memory()));
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assert_eq!(m.cpu(), &before);
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assert_eq!(m.cycles(), cycles);
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assert_eq!(m.last_timing(), timing);
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assert_eq!(m.halted(), ie == 0);
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let expected = if ie == 0 {
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StepKind::HaltIdle
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} else if ime != 0 && !masked {
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StepKind::IrqEntry
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} else {
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StepKind::Instruction
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};
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assert_eq!(m.step().unwrap(), expected);
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}
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}
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}
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}
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#[test]
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fn pending_keypad_request_wakes_on_ie_enable_and_ack_does_not_restore_halt() {
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let mut m = machine(false);
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m.memory_mut().write16(KEYCNT, 0x4001).unwrap();
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m.memory_mut().write8(HALTCNT, 0).unwrap();
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press(m.memory_mut(), 1);
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assert!(m.halted());
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m.memory_mut().write16(IE, IRQ).unwrap();
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assert!(!m.halted());
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ack(m.memory_mut());
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assert!(!m.halted());
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assert_eq!(m.step().unwrap(), StepKind::Instruction);
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}
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#[test]
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fn control_write_can_wake_halt_with_an_already_held_key() {
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let mut m = machine(false);
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press(m.memory_mut(), 1);
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m.memory_mut().write16(IE, IRQ).unwrap();
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m.memory_mut().write8(HALTCNT, 0).unwrap();
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m.memory_mut().write16(KEYCNT, 0x4001).unwrap();
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assert!(!m.halted());
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assert_eq!(m.step().unwrap(), StepKind::Instruction); // IME remains zero.
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}
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#[test]
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fn keypad_irq_entry_and_return_restore_arm_and_thumb_instruction_state() {
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for thumb in [false, true] {
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let rom = if thumb {
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let mut code = words(&[0xe28f_0001, 0xe12f_ff10]);
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code.extend(0x2107_u16.to_le_bytes());
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code
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} else {
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words(&[0xe3a0_1007])
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};
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let bios = 0xe25e_f004_u32.to_le_bytes().repeat(BIOS_SIZE / 4);
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let mut mem = Memory::with_bios(rom, bios).unwrap();
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let mut cpu = Cpu::new(ROM_START);
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if thumb {
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cpu.step(&mut mem).unwrap();
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cpu.step(&mut mem).unwrap();
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}
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let pc = cpu.pc();
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let status = cpu.cpsr();
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mem.write16(KEYCNT, 0x4001).unwrap();
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mem.write16(IE, IRQ).unwrap();
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mem.write16(IME, 1).unwrap();
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press(&mut mem, 1);
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let mut m = Machine::new(cpu, mem);
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assert_eq!(m.step().unwrap(), StepKind::IrqEntry);
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assert_eq!(m.cpu().mode(), Mode::Irq);
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assert_eq!(m.cpu().spsr(), Some(status));
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assert_eq!(m.cpu().registers()[14], pc + 4);
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assert!(pending(m.memory()));
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ack(m.memory_mut());
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m.step().unwrap();
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assert_eq!(m.cpu().pc(), pc);
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assert_eq!(m.cpu().cpsr(), status);
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assert_eq!(
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m.cpu().instruction_set(),
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if thumb {
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InstructionSet::Thumb
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} else {
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InstructionSet::Arm
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}
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);
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m.step().unwrap();
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assert_eq!(m.cpu().registers()[1], 7);
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}
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}
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fn prepared(instruction: u32, destination: u32, value: u32) -> Machine {
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let mut mem = Memory::new(words(&[
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0xe59f_0008,
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0xe59f_1008,
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instruction,
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0xeaff_fffe,
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destination,
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value,
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]))
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.unwrap();
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let mut cpu = Cpu::new(ROM_START);
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cpu.step(&mut mem).unwrap();
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cpu.step(&mut mem).unwrap();
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Machine::new(cpu, mem)
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}
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#[test]
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fn cpu_store_samples_keys_then_irq_enters_on_the_following_step() {
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for (instruction, address, value) in [
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(0xe1c0_10b0, KEYCNT, 0x4001),
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(0xe580_1000, KEYINPUT, 0x4001_ffff),
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] {
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let mut m = prepared(instruction, address, value);
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press(m.memory_mut(), 1);
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m.memory_mut().write16(IE, IRQ).unwrap();
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m.memory_mut().write16(IME, 1).unwrap();
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assert_eq!(m.step().unwrap(), StepKind::Instruction);
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assert_eq!(m.cpu().pc(), ROM_START + 12);
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assert_eq!(m.memory().read16(KEYCNT).unwrap(), 0x4001);
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assert_eq!(m.memory().read16(KEYINPUT).unwrap(), 0x3fe);
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assert_eq!(m.step().unwrap(), StepKind::IrqEntry);
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}
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}
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#[test]
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fn failed_block_store_does_not_commit_key_control_irq_history_or_halt_wake() {
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||||
// STMIA r0!,{r1,r2}: keypad word is valid, next word (serial RCNT) is not mapped.
|
||||
let mut m = prepared(0xe8a0_0006, KEYINPUT, 0x4001_0000);
|
||||
press(m.memory_mut(), 1);
|
||||
m.memory_mut().write16(IE, IRQ).unwrap();
|
||||
let before = m.cpu().clone();
|
||||
let cycles = m.cycles();
|
||||
let timing = m.last_timing();
|
||||
assert_eq!(
|
||||
m.step(),
|
||||
Err(MachineError::Cpu(CpuError::Memory(MemoryError::Unmapped(
|
||||
KEYINPUT + 4
|
||||
))))
|
||||
);
|
||||
assert_eq!(m.cpu(), &before);
|
||||
assert_eq!(m.cycles(), cycles);
|
||||
assert_eq!(m.last_timing(), timing);
|
||||
assert_eq!(m.memory().read16(KEYCNT).unwrap(), 0);
|
||||
assert!(!pending(m.memory()));
|
||||
m.memory_mut().write8(HALTCNT, 0).unwrap();
|
||||
assert!(m.halted());
|
||||
m.memory_mut().write16(KEYCNT, 0xc001).unwrap();
|
||||
assert!(pending(m.memory())); // Failure did not consume the first AND sample.
|
||||
assert!(!m.halted());
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn dma_control_write_samples_once_and_ready_dma_precedes_irq() {
|
||||
for word in [false, true] {
|
||||
let mut m = machine(false);
|
||||
press(m.memory_mut(), 1);
|
||||
m.memory_mut().write16(IE, IRQ).unwrap();
|
||||
m.memory_mut().write16(IME, 1).unwrap();
|
||||
let value = if word { 0x4001_ffff } else { 0x4001 };
|
||||
m.memory_mut().write32(0x0200_0000, value).unwrap();
|
||||
m.memory_mut().write32(DMA_BASE, 0x0200_0000).unwrap();
|
||||
m.memory_mut()
|
||||
.write32(DMA_BASE + 4, if word { KEYINPUT } else { KEYCNT })
|
||||
.unwrap();
|
||||
// Fixed destination, two units. IRQ from first unit must wait for second.
|
||||
m.memory_mut()
|
||||
.write32(DMA_BASE + 8, if word { 0x8440_0002 } else { 0x8040_0002 })
|
||||
.unwrap();
|
||||
let before = m.cpu().clone();
|
||||
assert_eq!(m.step().unwrap(), StepKind::Dma { channel: 0 });
|
||||
assert!(pending(m.memory()));
|
||||
assert_eq!(m.cpu(), &before);
|
||||
assert_eq!(m.step().unwrap(), StepKind::Dma { channel: 0 });
|
||||
assert_eq!(m.cpu(), &before);
|
||||
assert_eq!(m.step().unwrap(), StepKind::IrqEntry);
|
||||
}
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn keypad_and_timer_requests_coexist_and_acknowledge_independently() {
|
||||
let mut m = bus();
|
||||
m.write32(TIMER_BASE, 0x00c0_ffff).unwrap();
|
||||
m.advance_cycles(1);
|
||||
m.write16(TIMER_BASE + 2, 0).unwrap();
|
||||
m.write16(KEYCNT, 0x4001).unwrap();
|
||||
press(&mut m, 1);
|
||||
assert_eq!(m.read16(IF).unwrap(), IRQ | 8);
|
||||
ack(&mut m);
|
||||
assert_eq!(m.read16(IF).unwrap(), 8);
|
||||
press(&mut m, 1);
|
||||
m.write16(IF, 8).unwrap();
|
||||
assert_eq!(m.read16(IF).unwrap(), IRQ);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn original_bios_intrwait_can_sleep_until_keypad_callback_records_the_request() {
|
||||
let rom = words(&[0xe3a0_0001, 0xe3a0_1a01, 0xef04_0000, 0xeaff_fffe]);
|
||||
let mut m = bios::boot(rom).unwrap();
|
||||
for _ in 0..100 {
|
||||
if m.cpu().pc() == ROM_START + 8 {
|
||||
break;
|
||||
}
|
||||
m.step().unwrap();
|
||||
}
|
||||
assert_eq!(m.cpu().pc(), ROM_START + 8);
|
||||
let before = m.cpu().clone();
|
||||
let callback = words(&[
|
||||
0xe280_0c02,
|
||||
0xe1d0_10b2,
|
||||
0xe1c0_10b2,
|
||||
0xe59f_2010,
|
||||
0xe1d2_30b0,
|
||||
0xe183_3001,
|
||||
0xe1c2_30b0,
|
||||
0xe12f_ff1e,
|
||||
0xe1a0_0000,
|
||||
bios::IRQ_FLAGS,
|
||||
]);
|
||||
for (i, byte) in callback.into_iter().enumerate() {
|
||||
m.memory_mut().write8(0x0300_1000 + i as u32, byte).unwrap();
|
||||
}
|
||||
m.memory_mut()
|
||||
.write32(bios::IRQ_HANDLER, 0x0300_1000)
|
||||
.unwrap();
|
||||
m.memory_mut().write16(KEYCNT, 0x4001).unwrap();
|
||||
m.memory_mut().write16(IE, IRQ).unwrap();
|
||||
for _ in 0..200 {
|
||||
if m.halted() {
|
||||
break;
|
||||
}
|
||||
m.step().unwrap();
|
||||
}
|
||||
assert!(m.halted());
|
||||
press(m.memory_mut(), 1);
|
||||
assert!(!m.halted());
|
||||
let mut irq_entries = 0;
|
||||
for _ in 0..300 {
|
||||
if m.cpu().pc() == ROM_START + 12 {
|
||||
break;
|
||||
}
|
||||
if m.step().unwrap() == StepKind::IrqEntry {
|
||||
irq_entries += 1;
|
||||
}
|
||||
}
|
||||
assert_eq!(irq_entries, 1);
|
||||
assert_eq!(m.cpu().pc(), ROM_START + 12);
|
||||
assert_eq!(m.cpu().cpsr(), before.cpsr());
|
||||
assert_eq!(&m.cpu().registers()[..15], &before.registers()[..15]);
|
||||
assert_eq!(m.memory().read16(IF).unwrap(), 0);
|
||||
assert_eq!(m.memory().read16(bios::IRQ_FLAGS).unwrap(), 0);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue