feat(audio): implement nominal Direct Sound playback and FIFO DMA
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@ -53,9 +53,12 @@ The repository is a Cargo workspace with three crates:
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| `crates/gba-core/src/cpu/fetch_history_tests.rs` | Shared sample consumption, no execution-entry rereads, and failed-step retry |
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| `crates/gba-core/src/cpu/fetch_boundary_tests.rs` | Actual fetch-region snapshots, split refills, IWRAM lane requirements, ROM-window boundaries, and nominal timing |
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| `crates/gba-core/src/io.rs` | I/O registers, timers, HALT/STOP wake-up, next-event bounds, and IRQ latches |
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| `crates/gba-core/src/io/inactive.rs` | Disabled sound and disconnected serial initialization with explicit unsupported-activity validation |
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| `crates/gba-core/src/audio.rs` | Direct Sound FIFO/playback state, idle PSG/wave banks, and instantaneous stereo mixing |
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| `crates/gba-core/tests/direct_sound.rs` | FIFO lanes/reset, signed mixing, timer selection, DMA refill, and HALT/STOP |
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| `crates/gba-core/src/memory/audio_step_tests.rs` | Audio access phases, shadow validation, and CPU/DMA failure rollback |
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| `crates/gba-core/src/io/inactive.rs` | Disconnected serial initialization with explicit unsupported-activity validation |
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| `crates/gba-core/tests/inactive_devices.rs` | Device masks, wave RAM, GPIO pull-ups, serial data, and failed CPU/DMA write isolation |
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| `crates/gba-core/src/io/timer_step.rs` | Staged timer bank, shared divider phase, and timer IF bits at ordered CPU/DMA bus phases |
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| `crates/gba-core/src/io/timer_step.rs` | Staged timer/audio state, divider phase, timer IF bits, and sound refill requests at ordered CPU/DMA bus phases |
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| `crates/gba-core/src/memory/timer_step_tests.rs` | Timer access phases, coherent lanes, cascades, IF ordering, rollback, DMA, idle, and clock ownership |
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| `crates/gba-core/src/display.rs` | Display clock, scanline status, comparison edges, and display IRQ events |
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| `crates/gba-core/src/dma.rs` | DMA registers, internal pointers, retained channel data, trigger state, priority, and completion IRQs |
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@ -1,49 +1,112 @@
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# Sound initialization subset
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# Direct Sound subset
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Sound synthesis and host audio output are not implemented.
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The core now models disabled sound-register state so firmware can perform a functional sound reset.
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This is not a silent-audio compatibility mode. Enabling sound returns an explicit diagnostic.
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The core models timer-driven Direct Sound A/B playback and a bounded sound-DMA configuration.
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It does not produce desktop audio. Programmable sound generator (PSG) synthesis remains unsupported.
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`Memory::audio_level()` exposes the current digital stereo level for deterministic inspection, not a continuous sample stream.
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## Supported state
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## Registers and inactive PSG state
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| Address | Behavior |
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| --- | --- |
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| `0x04000060..0x04000081` | Programmable sound generator (PSG) registers remain zero; writes have no effect while master sound is disabled |
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| `0x04000082` (`SOUNDCNT_H`) | Retains mixing/routing/timer configuration with readback mask `0x770f` |
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| `0x04000084` (`SOUNDCNT_X`) | Reads zero; status flags are read-only; a write setting bit 7 fails |
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| `0x04000088` (`SOUNDBIAS`) | Retains bias/resolution configuration with mask `0xc3fe`; no analog output is generated |
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| `0x04000090..0x0400009f` | Read/write wave RAM in the CPU-accessible inactive bank |
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| `0x04000060..0x04000081` | Idle PSG configuration and documented read masks; writes are ignored while master sound is disabled |
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| `0x04000082` (`SOUNDCNT_H`) | Mixing, routing, timer selection, and FIFO reset strobes; readback mask `0x770f` |
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| `0x04000084` (`SOUNDCNT_X`) | Master enable in bit 7; read-only PSG activity flags remain zero |
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| `0x04000088` (`SOUNDBIAS`) | Bias/resolution configuration with mask `0xc3fe` |
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| `0x04000090..0x0400009f` | CPU wave RAM window, opposite the bank selected by `SOUND3CNT_L` bit 6 |
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| `0x040000a0..0x040000a7` | FIFO A/B writes with byte, halfword, and word access boundaries preserved |
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Unused mapped bytes through `0x0400008b` read zero and ignore writes.
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The FIFO reset strobes in `SOUNDCNT_H` do not latch. No FIFO data can be queued in this subset.
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FIFO addresses and the remaining sound-region holes stay unmapped.
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All sound configuration starts at zero in raw memory. RegisterRamReset bit 6 sets the functional bias default to `0x0200`.
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Unused mapped register bytes read zero and ignore writes.
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FIFO reads and the `0x0400008c..0x0400008f` gap remain explicit unmapped-access errors; no FIFO open-bus value is invented.
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Raw memory starts with zero sound state. RegisterRamReset bit 6 sets the functional bias default to `0x0200`.
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With master sound disabled, `SOUND3CNT_L` stays zero. The CPU accesses wave bank 1.
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Bank 0 cannot be selected or played and remains zero. Disabling master sound does not erase wave RAM.
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The BIOS reset explicitly clears the accessible wave RAM through ordinary stores.
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Future bank switching and channel playback need a complete sound engine, not a larger register array.
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Master disable clears PSG configuration and the FIFO queues, but retains wave RAM and Direct Sound routing/bias.
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The CPU then accesses wave bank 1. Idle bank selection can expose bank 0 after master enable.
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The original BIOS reset clears bank 1 and both FIFO queues. It retains bank 0 and any separate in-flight playback word.
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This is a functional reset subset, not a claim of complete firmware ordering or sound-reset equivalence.
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## Diagnostics and atomicity
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An enabled PSG channel trigger returns `MemoryError::UnsupportedIo` with the exact address and value.
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This applies even when the configured channel would be inaudible. Disabled PSG trigger writes are ignored.
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Length, envelope, sweep, frequency, and wave-bank playback clocks are not implemented.
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Do not interpret successful idle configuration writes as PSG synthesis.
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A write setting `SOUNDCNT_X` bit 7 returns `MemoryError::UnsupportedIo`, including the address, byte value, and operation.
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Status bits and unused bits alone do not enable sound.
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Validation occurs before any bytes in the access are written.
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Block stores validate every register value before committing earlier writes. Failed CPU and DMA steps remain retryable.
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## FIFO and timer behavior
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Original tests cover disabled-register writes, masks, byte lanes, wave retention, and BIOS reset selection.
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They also check rejected sound activation through byte/word accesses, ARM block stores, and DMA without partial state changes.
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Each channel has a seven-word queue, a separate four-byte playback word, and a held signed sample.
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Timer 0 or timer 1 overflow clocks the selected channel while master sound is enabled.
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Timer 1 cascade overflows work. Timer IRQ enable and stereo routing do not gate sample consumption.
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Timers 2 and 3 cannot clock Direct Sound.
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## Remaining work
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On each selected overflow:
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Implement channel clocks, length/envelope/sweep state, wave banking, FIFO consumption, timer-triggered sound DMA, and mixing.
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Add a host-independent sample interface before connecting a desktop audio backend.
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Do not acknowledge active sound requests without implementing their device behavior.
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1. Request sound DMA if the queue contains at most three words, before loading a playback word.
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2. Load a queued word if the playback word is empty.
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3. Latch the next signed eight-bit sample in little-endian order.
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The held sample remains unchanged between overflows. An empty playback word supplies zero on the next overflow.
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This underflow policy follows both consulted emulator implementations; the cited hardware report leaves it uncertain.
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A bulk advance consumes all available samples and then reaches zero without looping over every empty overflow.
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A partial FIFO write updates the addressed lanes of the next queue slot and enqueues that whole word.
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Other lanes retain that slot's previous bytes. A write to a full queue clears the queue.
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Reset strobes clear queues without changing the held sample or remaining playback bytes.
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Queue clearing also zeros stored queue slots in this nominal model.
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Exact stale-lane behavior across overflow/reset remains unverified on hardware.
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HALT continues timer/audio progress. STOP freezes it.
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Master disable stops sample consumption; route disable only mutes the mixer path.
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## Sound DMA
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Special timing supports DMA1 to FIFO A and DMA2 to FIFO B.
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Each request transfers four 32-bit words with a fixed destination, regardless of programmed count, width, or destination mode.
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Source address control, channel priority, repeat enable, completion IRQ, and retained DMA data still apply.
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Without repeat, the channel disables after the fourth word. With repeat, it waits for another timer request.
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Other channel/FIFO pairings and non-FIFO destinations remain explicit `DmaError::UnsupportedControl` cases.
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The references disagree about request routing outside the supported pairing; hardware reports permit non-FIFO destinations.
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The core does not silently guess those configurations. Video capture and Game Pak DRQ remain unsupported.
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Requests become visible at successful machine-step boundaries. Active DMA blocks ignore further requests.
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Device-only bulk advances coalesce unserviced requests; they do not execute or replay DMA blocks.
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Sub-instruction DMA arbitration and exact refill latency are not modeled.
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## Mixing and timing ownership
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Each routed sample contributes `sample * 2` at 50% volume or `sample * 4` at 100% volume.
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The mixer adds the ten-bit bias, clips each side to `0..1023`, and subtracts 512.
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`StereoLevel` therefore contains signed levels in `-512..511`. Master disable returns zero.
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Bias resolution bits retain their values but do not yet drive pulse-width modulation (PWM) sampling or quantization.
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There is no resampling, analog filtering, sample queue, or host output backend.
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Polling once per video frame will not reconstruct audio.
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Timer and sound state share the staged CPU/DMA clock.
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Reads and writes observe their nominal bus-completion phase, after earlier timer overflows.
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Successful steps commit once. Failed steps discard FIFO consumption, held samples, register writes, and refill requests.
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Block-store validation simulates sound enable/disable in a temporary state before committing any RAM or I/O writes.
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Other devices retain their existing scheduling limits.
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## Validation and remaining work
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Original tests cover signed samples, byte order, queue capacity, partial writes, resets, underflow, stereo routing, and clipping.
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They also cover cascaded timers, DMA block/repeat behavior, source progress, completion IRQs, HALT/STOP, and clock batching.
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CPU/DMA failure tests verify transactional rollback and sound writes at bus completion.
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BIOS tests cover disabled FIFO reset and the supported wave-bank policy.
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These tests validate the documented nominal model, not hardware audio fidelity.
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Next work: PSG clocks and synthesis, a timestamped or fixed-rate output stream, PWM/mixer sampling, and a Darwin host backend.
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The local Emerald startup now passes master enable and stops at a PSG channel 1 trigger.
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See [the local runtime result](../research/emerald-reset.md).
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## References
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- [GBATEK sound control registers](https://problemkaputt.de/gbatek-gba-sound-control-registers.htm): disabled PSG behavior, master enable, masks, FIFO reset strobes, and bias.
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- [GBATEK](https://mgba-emu.github.io/gbatek/): channel 3 wave-bank access and register layout.
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- [mGBA BIOS service implementation at 3a5e34be](https://github.com/mgba-emu/mgba/blob/3a5e34be33dc7f8f707e5bc9db69e8a430046f21/src/gba/bios.c): functional reset defaults. No upstream implementation was copied.
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- [GBATEK Direct Sound](https://problemkaputt.de/gbatek-gba-sound-channel-a-and-b-dma-sound.htm): registers, timer selection, signed samples, and DMA blocks.
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- [GBATEK sound control](https://problemkaputt.de/gbatek-gba-sound-control-registers.htm): master enable, read masks, reset strobes, routing, and bias.
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- [GBATEK mirror](https://mgba-emu.github.io/gbatek/): wave-bank access and register layout.
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- [gbadev Direct Sound overview](https://gbadev.net/gbadoc/audio/directsound.html): introductory FIFO/timer/DMA behavior; not authority for queue edge cases.
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- [Gericom's hardware findings, mGBA issue 1847](https://github.com/mgba-emu/mgba/issues/1847): seven-word queue, separate playback buffer, request order, partial writes, and overflow observations.
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- [mGBA audio at 3a5e34be](https://github.com/mgba-emu/mgba/blob/3a5e34be33dc7f8f707e5bc9db69e8a430046f21/src/gba/audio.c): playback, reset, mixing, and destination-based request routing comparison.
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- [NanoBoyAdvance APU at 55b5cf0a](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/hw/apu/apu.cc): master gating, playback word, underflow, and mixing.
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- [NanoBoyAdvance FIFO](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/hw/apu/channel/fifo.hh), [registers](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/hw/apu/registers.cc), and [DMA](https://github.com/nba-emu/NanoBoyAdvance/blob/55b5cf0ae3d929582ac5bfd486558173502b8354/src/nba/src/hw/dma/dma.cc): queue/reset policy and channel-based request routing comparison.
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- [mGBA BIOS at 3a5e34be](https://github.com/mgba-emu/mgba/blob/3a5e34be33dc7f8f707e5bc9db69e8a430046f21/src/gba/bios.c): functional reset defaults.
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Reset values are source-backed. Exact Nintendo firmware ordering, timing, and analog behavior are not established.
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The Rust implementation and regression programs are original. No upstream implementation or external test ROM was copied into the repository.
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@ -216,11 +216,12 @@ Supported flags can be combined:
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| 3 | Clear all 96 KiB of video RAM: `0x06000000..0x06017fff` |
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| 4 | Clear sprite attribute memory (OAM): `0x07000000..0x070003ff` |
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| 5 | Reset supported idle serial state and select general-purpose inputs |
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| 6 | Reset disabled sound state, mixing control, bias, and accessible wave RAM |
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| 6 | Disable sound, reset FIFO queues and mixing control, set bias, and clear accessible wave bank 1 |
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| 7 | Reset supported display, DMA, timer, and interrupt registers as described below |
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All low-byte flag combinations, including `r0=0xff`, are accepted within the supported device subset.
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This is not full audio or serial support. [Sound activation](audio.md) and [serial transfers](serial.md) still fail explicitly.
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This is not full audio or serial support. [PSG playback](audio.md) and [serial transfers](serial.md) still fail explicitly.
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Sound reset retains wave bank 0 and the separate in-flight playback word; exact firmware sound-reset equivalence is not established.
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The firmware always clears the low halfword of SIODATA32, even when bit 5 is clear; its upper halfword is preserved.
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Every supported request first writes `DISPCNT=0x0080`, including requests with no selected flags.
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@ -509,5 +510,5 @@ Unsupported SWIs, unsupported exception vectors, and null/misaligned IRQ callbac
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The CPU reports `CpuError::UnsupportedInstruction` with `bios::UNSUPPORTED_TRAP`, rather than silently treating a service as a no-op.
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Invalid arithmetic/decompression arguments use the same CPU error type with the distinct `bios::INVALID_ARGUMENT_TRAP` instruction.
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Prior boot/service steps remain committed on failure.
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Active sound, serial transfers, HardReset, and serial/Game Pak STOP wake-up remain unimplemented.
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PSG playback, host audio output, serial transfers, HardReset, and serial/Game Pak STOP wake-up remain unimplemented.
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This subset is not sufficient for Pokémon Emerald compatibility.
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@ -59,7 +59,9 @@ Exact startup/completion placement remains nominal, not independently verified p
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See [CPU resume timing](cpu.md#nominal-cpu-resume-after-dma) for failure, idle, and refill rules.
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Startup scheduling delays, channel-resumption costs, a full CPU fetch pipeline, and display-bus contention remain unmodeled.
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Special timing modes (sound FIFO/video capture), Game Pak DRQ, and prohibited source mode 3 return `DmaError::UnsupportedControl`.
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Special timing supports DMA1/FIFO A and DMA2/FIFO B with four-word blocks, forced word width, and fixed destinations.
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Timer-driven requests, repeat, and completion IRQs are described in [Direct Sound](audio.md).
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Other special-mode pairings, video capture, Game Pak DRQ, and prohibited source mode 3 return `DmaError::UnsupportedControl`.
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DMA reads below work RAM reuse known channel data as described below. They never expose BIOS bytes.
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DMA writes to DMA registers return `DmaError::RegisterDestination`; self-modifying transfers are not supported.
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Other accesses use the existing memory map, alignment checks, mirrors, and I/O write rules.
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@ -7,7 +7,7 @@
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Otherwise it services one ready DMA data unit, keeping the CPU paused.
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If HALT is waiting and no DMA is ready, it advances device clocks to the next event without executing CPU code.
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Otherwise, it samples the IRQ line, including the CPU's interrupt mask, then enters IRQ mode or executes one instruction.
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Each successful step advances display and timer clocks by its nominal cost.
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Each successful step advances display, timer, and Direct Sound clocks by its nominal cost.
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`Machine::last_timing()` reports separate code, data, internal, and idle cycle totals for the last successful step.
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`StepTiming::idle_cycles` counts device-clock cycles during HALT; it does not count CPU work.
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IRQ entry is a separate step; the vector instruction runs on the following step.
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DMA resume can make the discarded fetch non-sequential. Missing discarded bytes do not prevent IRQ entry.
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See [refill timing](../research/refill-fetch-timing.md) for history effects and remaining limits.
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A device event during a step can trigger IRQ entry once no DMA is ready and CPU masks allow delivery.
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Timer accesses use ordered bus-completion phases. Other device writes still take effect before their bulk clock update.
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Timer and sound accesses use ordered bus-completion phases. Other device writes still take effect before their bulk clock update.
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`StepKind::Dma { channel }` identifies a DMA unit. `StepKind::HaltIdle` identifies one bounded HALT clock advance.
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`StepKind::StopIdle` identifies a stopped system with no clock progress.
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The other step kinds remain `Instruction` and `IrqEntry`.
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A later internal cycle can raise an acknowledged timer request again. Non-timer IF bits retain their existing behavior.
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IRQ delivery still waits until the next machine step. A committed timer request can wake HALT, but not STOP.
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Successful steps commit timers, the shared divider phase, and timer IF bits.
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Failed steps discard staged counters, divider progress, reload/control writes, and requests.
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Successful steps commit timers, the shared divider phase, timer IF bits, and Direct Sound state.
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Failed steps discard staged counters, divider progress, timer/audio writes, FIFO consumption, and requests.
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Display and other device clocks then advance once, without advancing timers again.
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Those devices still use the bulk scheduler. Mid-instruction display events, general bus arbitration, and IRQ synchronization delays remain unmodeled.
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Display and remaining devices still use the bulk scheduler. Mid-instruction display events, general bus arbitration, and IRQ synchronization delays remain unmodeled.
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[Direct Sound](audio.md) consumes selected timer overflows in the timer transaction; sound DMA requests commit at step boundaries.
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Host clock advances and HALT idle batches retain ordinary bulk timer advancement; STOP idle does not advance timers.
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The unchanged [prefetch cancellation probe](../research/prefetch-cancellation.md) now matches both published interval totals and actual timer samples.
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@ -92,7 +93,8 @@ See [prescaler evidence and original tests](../research/timer-prescaler.md).
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Hardware startup and register-write delays are still not modeled. Writes retain the immediate bus-completion policy.
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The shared-phase tests validate this bounded model, not absolute enable/reload edges on hardware.
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Audio events and interrupt sources other than timers, display events, DMA completion, and keypad input are not implemented.
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Timers 0 and 1 can clock Direct Sound playback and request FIFO DMA independently of timer IRQ enable.
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Interrupt sources other than timers, display events, DMA completion, and keypad input are not implemented.
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`--timer-demo` executes original ARM code that configures Timer 0, IE, and IME.
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The timer overflows after 16 supplied cycles and enters the original handler through vector `0x18`.
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@ -228,7 +230,7 @@ The current desktop demos do not enter STOP; the frontend does not yet provide a
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Only keypad wake-up is implemented. General-purpose serial and Game Pak wake sources require their missing external devices.
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Oscillator restart delays, exact entry/wake edges, and hardware-specific IF behavior remain unverified.
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There is no host-thread sleep, wall-clock accounting, or audio clock implementation.
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There is no host-thread sleep or wall-clock accounting. STOP freezes the emulated timer-driven audio clock.
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The graphics demo now uses the optional original BIOS replacement's VBlankIntrWait service.
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Its IRQ callback acknowledges VBlank and updates the BIOS RAM flag before the service returns.
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@ -9,10 +9,11 @@ No ROM bytes, extracted code, or assets were added to the repository.
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## General correction
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The core now provides a bounded [disabled sound](../hardware/audio.md) and [disconnected serial](../hardware/serial.md) initialization model.
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The reset correction introduced bounded sound and [disconnected serial](../hardware/serial.md) initialization models.
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The [sound model](../hardware/audio.md) now also supports timer-driven Direct Sound and bounded FIFO DMA.
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The BIOS performs reset through original ARM stores against that model.
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Bit 5 selects general-purpose input pins and clears supported serial reset registers.
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Bit 6 disables sound, clears mixing configuration and accessible wave RAM, and sets the functional bias default.
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Bit 6 disables sound, resets FIFO queues, clears mixing configuration and accessible wave RAM, and sets the functional bias default.
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The low halfword of SIODATA32 is cleared unconditionally, matching the documented BIOS side effect.
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This is not a game-specific bypass. Original ARM and Thumb callers exercise selected flags and the all-device request.
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@ -28,13 +29,18 @@ direnv exec . cargo run --locked --release -- --rom roms/pokemon-emerald.gba --s
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direnv exec . cargo run --locked --release -- --rom roms/pokemon-emerald.gba --window --frames 120
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```
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Both runs now pass the BIOS reset and stop at the game's sound activation write:
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The earlier reset-only implementation stopped at master sound enable (`0x04000084`, PC `0x082e0518`).
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After the Direct Sound increment, both runs pass that write and stop at an enabled PSG channel 1 trigger:
|
||||
|
||||
```text
|
||||
PC=0x082e0518
|
||||
unsupported sound master enable (audio engine not implemented): write 0x8f at 0x04000084
|
||||
Steps: 321159; instructions: 320647; IRQ entries: 0; DMA units: 512; HALT idle: 0
|
||||
Nominal cycles: 1038738
|
||||
PC=0x082e03bc
|
||||
unsupported PSG channel trigger (synthesis not implemented): write 0x80 at 0x04000065
|
||||
```
|
||||
|
||||
The native run captures three startup frames. Direct Sound behavior is validated by original tests, not by audible game output.
|
||||
|
||||
The native run captures startup frames before this diagnostic. These are not evidence of a working title screen or gameplay.
|
||||
The window run does not reach its requested frame limit and correctly exits with failure.
|
||||
Terminal execution is also diagnostic, not a compatibility pass.
|
||||
|
|
@ -46,9 +52,10 @@ Workspace debug/release tests, strict Clippy, public ARM/Thumb/memory/BIOS check
|
|||
Native ROM-window tests and graphics smoke modes pass on Darwin arm64.
|
||||
The pinned Pong debug/release reports match.
|
||||
|
||||
The next observed startup requirement is active audio-device behavior, starting at SOUNDCNT_X master enable.
|
||||
Implement channel/FIFO clocks, state, DMA requests, and an output interface before claiming sound support.
|
||||
Do not make enable succeed solely to suppress this diagnostic.
|
||||
The next observed startup requirement is PSG channel playback, beginning with pulse channel 1.
|
||||
Direct Sound now has FIFO clocks, nominal DMA requests, and an instantaneous digital-level inspection interface.
|
||||
A continuous sample stream and desktop output are still missing. Do not treat digital-level tests as audible-game validation.
|
||||
Do not suppress the PSG trigger diagnostic without implementing the requested device behavior.
|
||||
Cartridge saves remain a separate required feature. SRAM alone will not support Emerald's Flash save protocol.
|
||||
|
||||
Hardware and emulator references are recorded in the linked subsystem documents.
|
||||
|
|
|
|||
|
|
@ -78,7 +78,8 @@ Update this file when a feature lands or a limit is removed.
|
|||
- Raw ROM-file loading with original BIOS boot, terminal diagnostics, and final CPU/step reports.
|
||||
- Firmware boot initializes BG2/BG3 identity scales for bitmap and affine programs that do not program their own matrices.
|
||||
- RegisterRamReset supports disabled sound and disconnected serial initialization, including the common `r0=0xff` request.
|
||||
- Sound activation and unsupported serial operations produce explicit address/value diagnostics with whole-access and block-store rollback.
|
||||
- Direct Sound A/B support timer-driven FIFO playback, stereo digital levels, and DMA1/A or DMA2/B refill blocks.
|
||||
- PSG triggers and unsupported serial operations produce explicit address/value diagnostics with whole-access and block-store rollback.
|
||||
- ROM windows with scanline capture, keyboard input, focus-loss release, bounded execution slices, and interactive keypad wake from STOP.
|
||||
- Optional ROM-window frame limits and an original input-test ROM generator.
|
||||
- Headless JSON ROM suites with PC or VBlank completion, register/CPSR/memory/pixel assertions, scheduled buttons, bounded budgets, and structured failure reports.
|
||||
|
|
@ -134,8 +135,9 @@ Internal affine origins, vertical window flags, and vertical mosaic counters tra
|
|||
Horizontal window comparators retain four-cycle event history.
|
||||
Sprite rows prepare one line ahead with a whole-row cycle40 sample and nominal per-row work limits.
|
||||
Individual fetch timing, hardware-accurate work cutoffs, video-bus contention, and per-pixel color composition remain unimplemented.
|
||||
There is no sound synthesis, host audio output, or cartridge save support.
|
||||
The [sound initialization subset](hardware/audio.md) supports disabled register state and wave RAM; master sound enable remains diagnostic.
|
||||
There is no PSG synthesis, host audio output, or cartridge save support.
|
||||
The [Direct Sound subset](hardware/audio.md) supports FIFO/timer/DMA behavior, idle PSG state, wave banking, and instantaneous digital mixing.
|
||||
It does not yet provide a continuous sample stream. PSG playback and unverified sound-DMA pairings remain diagnostic.
|
||||
The [serial initialization subset](hardware/serial.md) supports idle normal data and disconnected general-purpose pins, not active transfers.
|
||||
Mapped I/O covers DMA, timers, interrupts, WAITCNT, display control/status, background control/scroll/affine registers, window/effect registers, KEYINPUT/KEYCNT, POSTFLG, and HALTCNT.
|
||||
Keypad IRQs use a documented polling model; hardware retrigger edges and asynchronous input timing remain unverified.
|
||||
|
|
@ -145,7 +147,8 @@ All named graphics demos connect desktop input and rendering to the emulated CPU
|
|||
ROM files can run in bounded terminal mode or a window with the original BIOS replacement.
|
||||
ROM windows have no demo-specific startup checks. Input is sampled between bounded execution slices.
|
||||
Audio, saves, and external BIOS loading remain unavailable. ROM loading does not establish commercial-game compatibility.
|
||||
A local Emerald run now completes its all-device reset and reaches sound activation at `0x04000084`, where it stops explicitly.
|
||||
A local Emerald run now completes its all-device reset and master sound enable.
|
||||
It stops explicitly at a PSG channel 1 trigger at `0x04000065`; no title-screen or gameplay compatibility is established.
|
||||
Its captured startup frames do not establish title-screen or gameplay compatibility. See [the startup result](research/emerald-reset.md).
|
||||
See [cartridge loading](hardware/cartridge.md) for file limits, step budgets, and exit status.
|
||||
The [ROM suite runner](rom-tests.md) has original regressions and a [pinned public ARM baseline](public-arm-tests.md).
|
||||
|
|
|
|||
|
|
@ -39,8 +39,9 @@ The [pinned Pong homebrew](public-pong.md) passes scripted menus, ball movement,
|
|||
The native Darwin window also starts and presents frames without a diagnostic.
|
||||
This exposed and corrected missing firmware affine-scale initialization, without a game-specific patch.
|
||||
Frame-based scenarios and the preparation adapter now make the result repeatable.
|
||||
A local Emerald run now passes its initial all-device reset and stops at sound master enable.
|
||||
See [the runtime result](research/emerald-reset.md). Active audio-device behavior is the next demonstrated startup requirement.
|
||||
A local Emerald run now passes its initial all-device reset and master sound enable, then stops at a PSG channel 1 trigger.
|
||||
The core has a tested Direct Sound subset, but no continuous sample stream or desktop audio output.
|
||||
See [the runtime result](research/emerald-reset.md). PSG playback is the next demonstrated startup requirement.
|
||||
The separate save requirement remains cartridge SRAM, followed by safe host save persistence.
|
||||
SRAM is byte-addressable battery-backed save memory. Flash and EEPROM remain separate protocols.
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue