feat(cpu): implement ARM7TDMI ARM and Thumb execution
Add ALU, transfers, banked status, exceptions, instruction timing, and CPU regression tests.
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0xrsydn
parent
85bc2de6e7
commit
535c69e09f
17 changed files with 4838 additions and 0 deletions
305
src/cpu/arm.rs
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305
src/cpu/arm.rs
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@ -0,0 +1,305 @@
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use super::{
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alu::{self, Shift},
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Cpu, CpuError,
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};
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use crate::memory::Memory;
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impl Cpu {
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pub(super) fn execute_arm(
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&mut self,
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instruction: u32,
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memory: &mut Memory,
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) -> Result<(), CpuError> {
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if instruction & 0x0f00_0000 == 0x0f00_0000 {
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self.enter_exception(super::Exception::SoftwareInterrupt);
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return Ok(());
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}
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if instruction & 0x0fbf_0fff == 0x010f_0000 {
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return self.read_status(instruction);
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}
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if instruction & 0x0fb0_fff0 == 0x0120_f000 || instruction & 0x0fb0_f000 == 0x0320_f000 {
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return self.write_status(instruction);
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}
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if instruction & 0x0fff_fff0 == 0x012f_ff10 {
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let target = self.operand_register((instruction & 15) as usize, 8);
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self.branch_exchange(target);
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return Ok(());
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}
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if instruction & 0x0e00_0000 == 0x0a00_0000 {
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let address = self.pc();
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let offset = (((instruction & 0x00ff_ffff) << 8) as i32 >> 6) as u32;
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if instruction & (1 << 24) != 0 {
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self.registers[14] = address.wrapping_add(4); // BL return address
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}
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self.registers[15] = address.wrapping_add(8).wrapping_add(offset);
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return Ok(());
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}
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if instruction & 0x0e00_0000 == 0x0800_0000 {
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return self.block_transfer(instruction, memory);
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}
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// SWP shares the 1001 low bits with multiply and halfword transfers.
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if instruction & 0x0fb0_0ff0 == 0x0100_0090 {
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return self.swap(instruction, memory);
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}
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if instruction & 0x0f80_00f0 == 0x0080_0090 {
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return self.multiply_long(instruction);
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}
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if instruction & 0x0fc0_00f0 == 0x0000_0090 {
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return self.multiply(instruction);
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}
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if instruction & 0x0e00_0090 == 0x0000_0090 {
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return self.halfword_transfer(instruction, memory);
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}
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if instruction & 0x0c00_0000 == 0x0400_0000 {
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return self.single_transfer(instruction, memory);
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}
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if instruction & 0x0c00_0000 == 0 {
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return self.data_processing(instruction);
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}
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Err(self.unsupported(instruction))
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}
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fn data_processing(&mut self, instruction: u32) -> Result<(), CpuError> {
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let opcode = (instruction >> 21) & 15;
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let set_flags = instruction & (1 << 20) != 0;
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let test = (8..=11).contains(&opcode);
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let source = ((instruction >> 16) & 15) as usize;
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let destination = ((instruction >> 12) & 15) as usize;
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// S=0 in the test/compare opcode range is PSR transfer or an extension.
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if test && !set_flags {
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return Err(self.unsupported(instruction));
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}
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let restore = if !test && destination == 15 && set_flags {
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Some(self.return_status(instruction)?)
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} else {
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None
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};
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let immediate = instruction & (1 << 25) != 0;
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let register_shift = !immediate && instruction & (1 << 4) != 0;
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let pc_offset = if register_shift { 12 } else { 8 };
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let (operand, carry) = if immediate {
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let rotation = ((instruction >> 8) & 15) * 2;
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let value = (instruction & 255).rotate_right(rotation);
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(
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value,
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if rotation == 0 {
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self.flags.carry
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} else {
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value >> 31 != 0
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},
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)
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} else {
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let amount = if register_shift {
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let shift_register = ((instruction >> 8) & 15) as usize;
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if instruction & (1 << 7) != 0 || shift_register == 15 {
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return Err(self.unsupported(instruction));
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}
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self.registers[shift_register] & 255
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} else {
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(instruction >> 7) & 31
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};
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alu::shift(
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self.operand_register((instruction & 15) as usize, pc_offset),
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Shift::decode(instruction >> 5),
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amount,
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self.flags.carry,
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register_shift,
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)
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};
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let (result, flags) = alu::execute(
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opcode,
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self.operand_register(source, pc_offset),
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operand,
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carry,
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self.flags,
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);
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if let Some((status, mode)) = restore {
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self.apply_status(status, mode);
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} else if set_flags {
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self.flags = flags;
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}
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let next = if !test && destination == 15 {
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self.instruction_set.align(result)
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} else {
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self.pc().wrapping_add(4)
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};
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if !test && destination != 15 {
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self.registers[destination] = result;
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}
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self.registers[15] = next;
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Ok(())
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}
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fn single_transfer(&mut self, instruction: u32, memory: &mut Memory) -> Result<(), CpuError> {
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let base_register = ((instruction >> 16) & 15) as usize;
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let destination = ((instruction >> 12) & 15) as usize;
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let pre = instruction & (1 << 24) != 0;
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let write_bit = instruction & (1 << 21) != 0;
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let write_back = !pre || write_bit;
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let byte = instruction & (1 << 22) != 0;
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let load = instruction & (1 << 20) != 0;
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if (!pre && write_bit) // LDRT/STRT access semantics are not implemented.
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|| (write_back && (base_register == 15 || (load && base_register == destination)))
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|| (byte && destination == 15)
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{
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return Err(self.unsupported(instruction));
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}
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let offset = if instruction & (1 << 25) != 0 {
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let rm = (instruction & 15) as usize;
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if instruction & (1 << 4) != 0 || rm == 15 {
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return Err(self.unsupported(instruction));
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}
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alu::shift(
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self.registers[rm],
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Shift::decode(instruction >> 5),
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(instruction >> 7) & 31,
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self.flags.carry,
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false,
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)
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.0
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} else {
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instruction & 0xfff
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};
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let base = self.operand_register(base_register, 8);
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let adjusted = offset_address(base, offset, instruction);
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let address = if pre { adjusted } else { base };
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let next = self.pc().wrapping_add(4);
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// All validation precedes memory writes. CPU changes follow successful access.
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let value = if load {
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if byte {
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u32::from(memory.read8(address)?)
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} else {
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memory.read32(address & !3)?.rotate_right((address & 3) * 8)
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}
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} else {
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let value = self.operand_register(destination, 12);
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if byte {
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memory.write8(address, value as u8)?;
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} else {
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memory.write32(address & !3, value)?;
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}
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value
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};
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if write_back {
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self.registers[base_register] = adjusted;
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}
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if load && destination != 15 {
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self.registers[destination] = value;
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}
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// ARMv4 LDR PC does not switch to Thumb, even if bit zero is set.
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self.registers[15] = if load && destination == 15 {
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value & !3
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} else {
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next
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};
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Ok(())
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}
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fn halfword_transfer(&mut self, instruction: u32, memory: &mut Memory) -> Result<(), CpuError> {
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let kind = (instruction >> 5) & 3;
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let load = instruction & (1 << 20) != 0;
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let pre = instruction & (1 << 24) != 0;
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let write_bit = instruction & (1 << 21) != 0;
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let write_back = !pre || write_bit;
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let base_register = ((instruction >> 16) & 15) as usize;
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let destination = ((instruction >> 12) & 15) as usize;
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if kind == 0
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|| (!load && kind != 1)
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|| (!pre && write_bit)
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|| destination == 15
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|| (write_back && (base_register == 15 || (load && base_register == destination)))
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{
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return Err(self.unsupported(instruction));
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}
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let offset = if instruction & (1 << 22) != 0 {
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((instruction >> 4) & 0xf0) | (instruction & 15)
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} else {
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let rm = (instruction & 15) as usize;
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if instruction & 0xf00 != 0 || rm == 15 {
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return Err(self.unsupported(instruction));
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}
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self.registers[rm]
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};
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let base = self.operand_register(base_register, 8);
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let adjusted = offset_address(base, offset, instruction);
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let address = if pre { adjusted } else { base };
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let value = if load {
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match kind {
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1 => u32::from(memory.read16(address & !1)?).rotate_right((address & 1) * 8),
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2 => memory.read8(address)? as i8 as i32 as u32,
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_ if address & 1 != 0 => memory.read8(address)? as i8 as i32 as u32,
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_ => memory.read16(address)? as i16 as i32 as u32,
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}
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} else {
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memory.write16(address & !1, self.registers[destination] as u16)?;
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0
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};
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if write_back {
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self.registers[base_register] = adjusted;
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}
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if load {
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self.registers[destination] = value;
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}
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self.registers[15] = self.pc().wrapping_add(4);
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Ok(())
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}
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fn multiply(&mut self, instruction: u32) -> Result<(), CpuError> {
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let rd = ((instruction >> 16) & 15) as usize;
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let rn = ((instruction >> 12) & 15) as usize;
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let rs = ((instruction >> 8) & 15) as usize;
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let rm = (instruction & 15) as usize;
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let accumulate = instruction & (1 << 21) != 0;
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if [rd, rn, rs, rm].contains(&15) || rd == rm || (!accumulate && rn != 0) {
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return Err(self.unsupported(instruction));
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}
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let mut result = self.registers[rm].wrapping_mul(self.registers[rs]);
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if accumulate {
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result = result.wrapping_add(self.registers[rn]);
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}
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self.registers[rd] = result;
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if instruction & (1 << 20) != 0 {
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self.flags.negative = result >> 31 != 0;
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self.flags.zero = result == 0;
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// ARM7 carry is unspecified after multiply; preserve it deterministically.
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}
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self.registers[15] = self.pc().wrapping_add(4);
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Ok(())
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}
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fn multiply_long(&mut self, instruction: u32) -> Result<(), CpuError> {
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let hi = ((instruction >> 16) & 15) as usize;
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let lo = ((instruction >> 12) & 15) as usize;
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let rs = ((instruction >> 8) & 15) as usize;
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let rm = (instruction & 15) as usize;
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if [hi, lo, rs, rm].contains(&15) || hi == lo || hi == rm || lo == rm {
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return Err(self.unsupported(instruction));
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}
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let mut result = if instruction & (1 << 22) != 0 {
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(i64::from(self.registers[rm] as i32) * i64::from(self.registers[rs] as i32)) as u64
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} else {
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u64::from(self.registers[rm]) * u64::from(self.registers[rs])
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};
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if instruction & (1 << 21) != 0 {
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let accumulator = (u64::from(self.registers[hi]) << 32) | u64::from(self.registers[lo]);
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result = result.wrapping_add(accumulator);
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}
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self.registers[hi] = (result >> 32) as u32;
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self.registers[lo] = result as u32;
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if instruction & (1 << 20) != 0 {
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self.flags.negative = result >> 63 != 0;
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self.flags.zero = result == 0;
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// Unspecified multiply C/V outputs are preserved, not hardware-verified.
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}
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self.registers[15] = self.pc().wrapping_add(4);
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Ok(())
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}
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}
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fn offset_address(base: u32, offset: u32, instruction: u32) -> u32 {
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if instruction & (1 << 23) != 0 {
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base.wrapping_add(offset)
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} else {
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base.wrapping_sub(offset)
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}
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}
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