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feat(cpu): retain ARM instruction pipeline words

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Buffer ARM sequential fetch results and refill target pairs after branches, PC writes, and machine exception entry. Stage advances transactionally, defer speculative fetch diagnostics, and preserve buffered words across CPU/DMA stores and host edits. Add explicit CPU pipeline invalidation for debugger repair and memory rebinding.

Add 15 original instruction-buffer regressions. Keep full-state rollback equality while distinguishing architectural comparisons in semantic tests. Update the display error test for an already buffered branch. Document evidence and separate remaining Thumb, bus-history, and timing work.

Validated on Darwin arm64: 967 workspace and 898 core/demo tests in each debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports and nominal cycles remain unchanged.
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0xrsydn 2026-10-06 03:57:57 +07:00
commit 47df9d05a7
24 changed files with 629 additions and 37 deletions
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docs/research/dma-resume-timing.md
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@ -44,7 +44,8 @@ A completed DMA WAITCNT store changes the settings before CPU resume.
## Limits
The model has no persistent fetch pipeline or per-access DMA arbitration.
The timing model has no per-access fetch scheduling or DMA arbitration.
The later [ARM instruction buffer](arm-instruction-buffer.md) retains instruction words but does not change these nominal costs.
It charges the current instruction address, not a separately scheduled PC+4/PC+8 pipeline fetch.
DMA still executes only between instructions, not between data accesses or during CPU internal cycles.