feat(cpu): retain ARM instruction pipeline words
Buffer ARM sequential fetch results and refill target pairs after branches, PC writes, and machine exception entry. Stage advances transactionally, defer speculative fetch diagnostics, and preserve buffered words across CPU/DMA stores and host edits. Add explicit CPU pipeline invalidation for debugger repair and memory rebinding. Add 15 original instruction-buffer regressions. Keep full-state rollback equality while distinguishing architectural comparisons in semantic tests. Update the display error test for an already buffered branch. Document evidence and separate remaining Thumb, bus-history, and timing work. Validated on Darwin arm64: 967 workspace and 898 core/demo tests in each debug/release profile, 39 Python tests, native ROM windows, ten window smoke modes, fmt, clippy, and rustdoc. Public ARM/Thumb/memory/BIOS reports and nominal cycles remain unchanged.
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@ -134,7 +134,8 @@ Missing BIOS images remain unmapped. The unused-memory ARM open-bus snapshot is
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The Thumb rule follows documented BIOS bus lanes and a source comparison with NanoBoyAdvance.
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See [Thumb BIOS prefetch research](../research/thumb-bios-prefetch.md) for evidence, emulator differences, and test scope.
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This models neither a persistent fetch pipeline nor exact refill, BIOS data-access, or DMA bus history.
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This BIOS readback model remains separate from the CPU's ARM instruction buffer.
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It does not model exact refill, BIOS data-access, or DMA bus history.
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The boundary diagnostic policy and precise bus timing remain hardware-unverified.
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Original regressions cover synthetic images, boot, exception returns, access widths, alignment, modes, and diagnostics.
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The [public BIOS ROM](../public-bios-tests.md) passes its unchanged protected-read assertions in debug and release builds.
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